Firestorm: SHA256SU1 measurements

Code:

  sha256su1 v0.4s, v1.4s, v2.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	0	0	61	1901	25	1000	1000	1000	104500	3018	3037	3037	2739	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2920	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	1901	25	1000	1000	1000	104500	3018	3037	3037	2739	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2920	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	82	1901	25	1000	1000	1000	104500	3054	3037	3037	2739	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2920	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	61	1901	25	1000	1000	1000	104500	3018	3037	3037	2739	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2920	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	1901	25	1000	1000	1000	104500	3018	3037	3037	2739	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2920	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	1901	25	1000	1000	1000	104500	3018	3037	3037	2739	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	1	0	73	1	16	1	1	2920	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	61	1901	25	1000	1000	1000	104500	3018	3037	3037	2739	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2920	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	61	1901	25	1000	1000	1000	104500	3018	3037	3037	2739	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2920	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	61	1901	25	1000	1000	1000	104500	3018	3037	3037	2739	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2920	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	61	1901	25	1000	1000	1000	104500	3018	3037	3037	2739	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2920	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  sha256su1 v0.4s, v1.4s, v2.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	61	19901	25	10100	100	10000	100	10000	500	1067500	1	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	0	3	16	2	2	29920	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	19901	25	10100	100	10000	100	10000	500	1067500	1	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	0	2	16	2	2	29920	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	19901	25	10100	100	10000	100	10000	500	1067500	0	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	29920	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	536	19901	25	10100	100	10000	100	10000	500	1067500	0	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	29920	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	441	19901	25	10100	100	10000	100	10000	500	1067500	0	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	29920	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	61	19901	25	10100	100	10000	100	10000	500	1067500	1	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	29920	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	61	19901	25	10100	100	10000	100	10000	500	1067500	0	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	3	29920	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	61	19901	25	10100	100	10000	100	10000	500	1067500	0	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	29920	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	726	19901	25	10100	100	10000	100	10000	500	1067500	0	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	29920	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	346	19901	25	10100	100	10000	100	10000	500	1067500	0	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	1	0	0	710	1	2	16	2	2	29920	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	145	19901	25	10010	10	10000	10	10000	50	1067500	0	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	640	2	17	2	2	29920	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	19901	25	10010	10	10000	10	10000	50	1067500	0	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	3	29920	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	19901	25	10010	10	10000	10	10000	50	1067500	0	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	640	3	16	2	2	29920	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	19901	25	10010	10	10000	10	10000	50	1067500	0	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	29920	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	19901	25	10010	10	10000	10	10000	50	1067500	0	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	29920	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	19901	25	10010	10	10000	10	10000	50	1067500	0	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	29920	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	19901	25	10010	10	10000	10	10000	50	1067500	0	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	29920	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	61	19901	25	10010	10	10000	10	10000	50	1067500	0	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	29920	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	61	19901	25	10010	10	10000	10	10000	50	1067500	0	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	3	2	29920	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	19901	25	10010	10	10000	10	10000	50	1067500	0	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	29920	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  sha256su1 v0.4s, v0.4s, v1.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	61	19901	25	10100	100	10000	100	10000	500	1067500	1	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	29920	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	19901	25	10100	100	10000	100	10000	500	1067500	1	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	29920	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	19901	25	10100	100	10000	100	10000	500	1067500	1	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	29920	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	528	61	19901	25	10100	100	10000	100	10000	500	1067500	1	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	29920	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	19901	25	10100	100	10000	100	10000	500	1067500	1	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	29920	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	61	19901	25	10100	100	10000	100	10000	500	1067500	1	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	29920	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	19901	25	10100	100	10000	100	10000	500	1067500	1	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	29920	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	19901	25	10100	100	10000	100	10000	500	1067500	1	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	1	710	1	16	1	1	29920	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	19901	25	10100	100	10000	100	10000	500	1067500	1	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	29920	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	19901	25	10100	100	10000	100	10000	500	1067500	0	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	29920	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	224	246	0	441	19901	25	10010	10	10000	10	10000	50	1067500	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	2	0	640	4	16	4	4	29920	10000	10	30038	30038	30038	30038	30038
10024	30037	225	6	0	61	19901	25	10010	10	10000	10	10000	50	1067500	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	5	16	5	5	29920	10000	10	30038	30038	30038	30038	30038
10024	30037	225	15	88	726	19901	25	10010	10	10000	10	10000	50	1067500	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30084	1	1	10021	10	9	10	10	10000	10	0	0	640	6	16	4	5	29920	10000	10	30038	30038	30038	30038	30038
10024	30037	225	6	0	61	19901	25	10010	10	10000	10	10000	50	1067500	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	6	16	5	6	29920	10000	10	30038	30038	30038	30038	30038
10024	30037	225	3	0	156	19901	25	10010	10	10000	10	10000	50	1067500	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	5	16	6	5	29920	10000	10	30038	30038	30038	30038	30038
10024	30037	225	6	0	82	19901	25	10010	10	10000	10	10000	50	1067500	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	6	16	6	6	29989	10000	10	30038	30038	30038	30038	30038
10024	30037	225	6	0	536	19901	25	10010	10	10000	10	10000	50	1067500	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	5	16	6	5	29920	10000	10	30038	30038	30038	30038	30038
10024	30037	225	15	0	61	19901	25	10010	10	10000	10	10000	50	1067500	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	6	16	6	5	29920	10000	10	30038	30038	30038	30038	30038
10024	30037	225	6	0	61	19901	25	10010	10	10000	10	10000	50	1067500	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	6	16	6	4	29920	10000	10	30038	30038	30038	30038	30038
10024	30037	225	60	0	82	19901	25	10010	10	10000	10	10000	50	1067500	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	5	16	6	6	29920	10000	10	30038	30038	30038	30038	30038

Test 4: Latency 1->3

Code:

  sha256su1 v0.4s, v1.4s, v0.4s

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	0	726	19901	25	10100	100	10000	100	10000	500	1067500	1	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29920	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	839	19901	25	10100	100	10000	100	10000	500	1067500	0	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29920	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	18	0	346	19901	25	10100	100	10000	100	10000	500	1067500	0	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29920	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	0	61	19901	25	10100	100	10000	100	10000	500	1067500	1	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29920	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	4	12	0	747	19901	25	10100	100	10000	100	10000	500	1067500	0	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30084	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29920	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	631	19901	25	10100	100	10000	100	10000	500	1067500	0	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29920	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	19901	25	10100	100	10000	100	10000	500	1067500	1	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29920	10000	100	30084	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	19901	25	10100	100	10000	100	10000	500	1067500	0	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29920	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	19901	25	10100	100	10000	100	10000	500	1067500	0	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29920	10000	100	30038	30038	30038	30038	30038
10204	30037	225	3	0	27	0	61	19901	25	10100	100	10000	100	10000	500	1067500	0	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29920	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	0	42	0	61	19901	25	10010	10	10000	10	10000	50	1067500	0	30018	30037	30037	28611	3	28767	10010	20	10000	20	30174	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	2	16	2	2	29920	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	9	0	61	19901	25	10010	10	10000	10	10000	50	1067500	0	30018	30037	30037	28611	3	28767	10010	20	10115	20	30171	30084	30037	4	1	10021	10	9	10	10	10000	10	3	4	2	1	0	4	7975	2	0	740	7	72	6	9	30063	2	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	19901	25	10010	10	10000	10	10000	50	1067500	0	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	2	16	2	2	29920	0	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	0	0	0	0	61	19901	25	10010	10	10000	10	10000	50	1067500	0	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	2	16	2	2	29920	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	19901	25	10010	10	10000	10	10000	50	1067500	0	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	1	0	0	0	0	640	2	16	2	2	29920	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	19901	25	10010	10	10000	10	10000	50	1067500	0	30018	30037	30037	28611	3	28767	10010	20	10000	20	30204	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	2	16	2	2	29920	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	19901	25	10010	10	10000	10	10000	50	1067500	0	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	2	16	2	2	29920	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	19901	25	10010	10	10000	10	10000	50	1067500	0	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	2	16	2	2	29920	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	19901	25	10010	10	10000	10	10000	50	1067500	0	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	2	16	2	2	29920	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	19901	25	10010	10	10000	10	10000	50	1067500	0	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	0	640	2	16	2	2	29920	0	10000	10	30038	30038	30038	30038	30038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  sha256su1 v0.4s, v8.4s, v9.4s
  movi v1.16b, 0
  sha256su1 v1.4s, v8.4s, v9.4s
  movi v2.16b, 0
  sha256su1 v2.4s, v8.4s, v9.4s
  movi v3.16b, 0
  sha256su1 v3.4s, v8.4s, v9.4s
  movi v4.16b, 0
  sha256su1 v4.4s, v8.4s, v9.4s
  movi v5.16b, 0
  sha256su1 v5.4s, v8.4s, v9.4s
  movi v6.16b, 0
  sha256su1 v6.4s, v8.4s, v9.4s
  movi v7.16b, 0
  sha256su1 v7.4s, v8.4s, v9.4s

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	80039	599	0	0	0	0	0	50	25	80100	100	80000	100	80000	500	640000	0	80020	80039	80039	59964	3	59997	80100	200	80000	200	240000	80039	80039	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	1	16	1	1	80035	0	160000	100	80040	80040	80040	80040	80040
160204	80039	600	0	0	0	0	0	50	25	80100	100	80000	100	80000	500	640000	1	80020	80039	80039	59964	3	59997	80100	200	80000	200	240000	80039	80039	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	1	16	1	1	80035	0	160000	100	80040	80040	80040	80040	80040
160204	80039	599	0	0	0	0	0	50	25	80100	100	80000	100	80000	500	640000	0	80020	80039	80039	59964	3	59997	80100	200	80000	200	240000	80039	80039	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	1	16	1	1	80035	0	160000	100	80040	80040	80040	80040	80040
160204	80039	599	0	0	0	0	0	50	25	80100	100	80000	100	80000	500	640000	0	80020	80039	80039	59964	3	59997	80100	200	80000	200	240000	80039	80039	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	1	16	1	1	80035	0	160000	100	80040	80040	80040	80040	80040
160204	80039	600	0	0	0	0	0	50	25	80100	100	80000	100	80000	500	640000	0	80020	80039	80039	59964	3	59997	80100	200	80000	200	240000	80039	80039	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	1	16	1	1	80035	0	160000	100	80040	80040	80040	80040	80040
160204	80039	600	0	0	0	0	0	50	25	80100	100	80000	100	80000	500	640000	0	80020	80039	80039	59964	3	59997	80148	200	80000	200	240000	80039	80039	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	1	16	1	1	80035	0	160000	100	80040	80040	80040	80040	80040
160204	80039	600	0	0	0	0	0	50	25	80100	100	80000	100	80000	500	640000	0	80020	80039	80039	59964	3	59997	80100	200	80000	200	240000	80039	80039	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	1	16	1	1	80035	0	160000	100	80040	80040	80040	80040	80040
160204	80039	599	0	0	0	0	0	715	25	80100	100	80000	100	80000	500	640000	0	80020	80039	80039	59964	3	59997	80100	200	80000	200	240000	80039	80039	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	1	16	1	1	80035	0	160000	100	80040	80040	80040	80040	80040
160204	80039	599	0	0	0	0	0	50	25	80100	100	80000	100	80000	500	640000	0	80020	80039	80039	59964	3	59997	80100	200	80000	200	240000	80039	80039	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	1	16	1	1	80035	0	160000	100	80040	80040	80040	80040	80040
160204	80039	599	0	0	0	0	0	50	25	80100	100	80000	100	80000	500	640000	0	80020	80039	80039	59964	3	59997	80100	200	80000	200	240000	80039	80039	1	1	160201	100	99	100	100	160000	100	0	0	0	10110	1	16	1	1	80035	0	160000	100	80040	80040	80040	80040	80040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	80039	599	0	0	0	0	0	56	25	80010	10	80000	10	80000	50	640000	0	1	80020	80039	80039	59986	3	60019	80010	20	80000	20	240000	80039	80039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	1	14	16	2	1	1	10	6	80035	0	20	13	160000	10	80040	80040	80040	80040	80040
160024	80039	599	0	0	0	0	0	56	25	80010	10	80000	10	80000	50	640000	1	1	80020	80039	80039	59986	3	60019	80010	20	80000	20	240000	80039	80039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	1	6	16	2	1	1	10	9	80035	0	20	13	160000	10	80040	80040	80040	80040	80040
160024	80039	599	0	0	0	0	0	56	25	80010	10	80000	10	80000	50	640000	0	1	80020	80039	80039	59986	3	60019	80010	20	80000	20	240000	80039	80039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	6	1	1	12	16	2	2	1	14	7	80035	0	40	117	160000	10	80040	80040	80040	80040	80040
160024	80039	599	0	0	0	0	0	56	25	80010	10	80000	10	80000	50	640000	2	1	80020	80039	80039	59986	3	60019	80010	20	80000	20	240000	80039	80039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	6	2	2	9	16	2	2	1	4	8	80035	0	20	26	160000	10	80040	80040	80040	80040	80040
160024	80039	599	0	0	0	0	0	56	25	80010	10	80000	10	80000	50	640000	1	1	80020	80039	80039	59986	3	60019	80010	20	80000	20	240000	80039	80039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	2	1	6	16	2	2	1	8	8	80035	0	40	13	160000	10	80040	80040	80040	80040	80040
160024	80039	600	0	0	0	0	0	56	25	80010	10	80000	10	80000	50	640000	0	1	80020	80039	80039	59986	3	60019	80010	20	80000	20	240000	80039	80039	1	1	160022	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	1	8	16	2	1	1	9	5	80035	0	20	13	160000	10	80040	80040	80040	80040	80040
160024	80039	599	0	0	0	0	0	56	25	80010	10	80000	10	80000	50	640000	2	1	80020	80039	80039	59986	3	60019	80010	20	80000	20	240000	80039	80039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	1	10	16	2	1	1	5	14	80035	0	20	13	160000	10	80040	80040	80040	80040	80040
160024	80039	600	0	0	0	0	0	56	25	80010	10	80000	10	80000	50	640000	1	1	80020	80039	80039	59986	3	60019	80010	20	80036	20	240438	80039	80039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	1	5	16	2	1	1	9	6	80035	0	20	13	160000	10	80040	80040	80040	80040	80040
160024	80039	599	0	0	0	0	0	56	25	80010	10	80000	10	80000	50	640000	1	1	80020	80039	80039	59986	3	60019	80010	20	80000	20	240000	80039	80039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	1	4	16	2	1	1	14	6	80035	0	20	13	160000	10	80040	80040	80040	80040	80040
160024	80039	600	0	0	0	0	0	246	25	80010	10	80000	10	80000	50	640000	1	1	80020	80039	80039	59986	3	60019	80010	20	80000	20	240000	80039	80039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	1	11	16	2	1	1	9	5	80035	0	20	13	160000	10	80040	80040	80040	80040	80040

Test 6: throughput

Count: 16

Code:

  sha256su1 v0.4s, v16.4s, v17.4s
  sha256su1 v1.4s, v16.4s, v17.4s
  sha256su1 v2.4s, v16.4s, v17.4s
  sha256su1 v3.4s, v16.4s, v17.4s
  sha256su1 v4.4s, v16.4s, v17.4s
  sha256su1 v5.4s, v16.4s, v17.4s
  sha256su1 v6.4s, v16.4s, v17.4s
  sha256su1 v7.4s, v16.4s, v17.4s
  sha256su1 v8.4s, v16.4s, v17.4s
  sha256su1 v9.4s, v16.4s, v17.4s
  sha256su1 v10.4s, v16.4s, v17.4s
  sha256su1 v11.4s, v16.4s, v17.4s
  sha256su1 v12.4s, v16.4s, v17.4s
  sha256su1 v13.4s, v16.4s, v17.4s
  sha256su1 v14.4s, v16.4s, v17.4s
  sha256su1 v15.4s, v16.4s, v17.4s

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0002

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	160237	1199	1	0	0	0	0	0	92	25	160100	100	160000	100	160000	500	1280000	0	160020	160039	160039	139964	0	3	139997	160100	200	160000	200	480000	160039	160039	1	1	160201	100	99	100	100	160000	100	0	0	0	26	2	60	0	0	10110	6	16	8	5	160035	7	160000	100	160040	160040	160040	160040	160040
160204	160236	1199	0	0	0	0	0	0	50	25	160100	100	160096	100	160000	500	1280000	0	160172	160039	160039	139964	0	3	139997	160221	200	160000	200	480000	160039	160039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10168	6	16	6	6	160035	0	160000	100	160040	160040	160040	160040	160040
160204	160039	1199	0	0	0	0	0	0	180	25	160206	102	160000	100	160000	500	1280812	0	160020	160039	160039	139964	0	3	139997	160100	200	160000	200	480000	160039	160039	4	1	160201	100	99	100	100	160000	100	2	0	0	0	0	0	0	0	10110	6	16	5	6	160035	0	160000	100	160040	160040	160237	160040	160040
160204	160039	1198	0	0	0	0	0	0	92	25	160100	100	160000	100	160000	500	1280000	0	160020	160039	160235	139964	0	3	139997	160100	200	160000	200	480000	160039	160039	2	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10110	5	16	5	5	160035	0	160000	100	160139	160040	160040	160040	160040
160204	160039	1199	0	0	0	0	0	0	50	25	160100	100	160000	100	160000	500	1280000	0	160020	160039	160039	139964	0	3	139997	160100	200	160000	200	480000	160039	160039	5	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10110	6	16	6	5	160035	0	160000	100	160040	160040	160040	160040	160040
160204	160039	1198	0	0	0	0	0	0	50	25	160100	100	160000	100	160000	500	1280000	0	160020	160039	160039	139964	0	3	139997	160100	200	160000	200	480447	160039	160039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	3	0	0	10110	6	16	10	5	160035	9	160000	100	160040	160040	160040	160239	160040
160204	160039	1199	1	0	0	0	0	0	715	25	160100	100	160000	100	160000	500	1280000	0	160020	160039	160039	139964	0	3	140143	160100	200	160000	200	480000	160039	160089	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	9	0	0	10110	5	16	6	6	160035	0	160000	100	160040	160040	160040	160040	160040
160204	160039	1199	0	0	0	0	12	352	50	25	160100	100	160000	100	160000	525	1280000	0	160020	160039	160039	139964	0	3	139997	160100	200	160000	200	480000	160039	160039	1	1	160201	100	99	100	100	160000	100	0	0	0	1	0	0	0	0	10110	5	16	4	4	160035	0	160000	100	160040	160040	160040	160040	160040
160204	160039	1199	1	0	0	0	12	352	50	25	160100	100	160000	100	160000	500	1280000	0	160020	160039	160039	139964	0	3	139997	160100	200	160000	200	480000	160239	160039	1	1	160201	100	99	100	100	160000	100	0	0	0	3	0	0	0	0	10167	5	16	6	5	160035	0	160000	100	160040	160040	160040	160040	160040
160204	160039	1199	0	0	0	0	582	0	50	25	160100	100	160000	100	160000	620	1280000	0	160020	160039	160039	139964	0	3	139997	160100	200	160000	200	480144	160039	160039	5	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10110	5	16	5	8	160035	0	160000	100	160040	160040	160040	160040	160040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0002

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	df	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	160039	1199	0	0	56	25	160010	10	160000	10	160000	50	1280000	1	1	160020	0	160039	160039	139986	0	3	140019	160010	20	160000	20	480000	160039	160039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10025	3	1	2	9	16	2	1	1	6	5	3	160034	15	13	160000	10	160040	160040	160040	160040	160040
160024	160039	1198	0	0	56	25	160010	10	160000	10	160000	50	1280000	1	1	160020	0	160039	160039	139986	0	3	140019	160010	20	160000	20	480000	160039	160039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	177	0	0	10025	3	1	1	5	16	2	1	1	9	3	3	160034	15	13	160000	10	160040	160040	160040	160040	160040
160024	160039	1199	0	0	56	25	160010	10	160000	10	160000	50	1280000	1	1	160020	0	160039	160039	139986	0	3	140019	160010	20	160000	20	480000	160039	160039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	375	0	0	10025	3	1	1	5	16	2	1	1	10	10	3	160034	15	13	160000	10	160040	160040	160040	160040	160040
160024	160039	1199	0	0	6657	25	160010	10	160000	10	160000	50	1280000	1	1	160020	0	160039	160039	139986	0	3	140019	160010	20	160000	20	480000	160039	160039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	348	0	0	10025	3	2	2	5	16	2	1	1	3	5	3	160147	15	13	160000	10	160040	160040	160040	160040	160040
160024	160285	1200	3	0	56	25	160010	10	160000	10	160000	50	1280000	0	1	160020	0	160039	160039	139986	0	3	140019	160010	20	160000	20	480000	160039	160039	1	1	160021	10	9	10	10	160000	10	2	0	0	2	3232	0	0	10025	3	1	1	4	16	2	1	1	9	3	3	160034	15	13	160000	10	160040	160040	160040	160040	160040
160024	160039	1199	0	0	721	25	160010	10	160000	10	160000	50	1280000	1	1	160020	0	160039	160039	139986	0	3	140019	160010	20	160000	20	480000	160039	160039	1	1	160021	10	9	10	10	160000	10	0	0	4	0	213	0	0	10025	3	1	1	4	16	2	1	1	8	9	3	160034	15	13	160000	10	160040	160040	160040	160040	160040
160024	160039	1198	0	0	77	25	160010	10	160000	10	160000	50	1280000	1	1	160020	0	160039	160039	139986	0	3	140019	160010	20	160000	20	480000	160039	160039	1	1	160021	10	9	10	10	160000	10	2	0	1	0	174	0	0	10025	3	1	1	3	16	2	1	1	3	9	3	160034	15	13	160000	10	160040	160040	160040	160040	160040
160024	160039	1199	0	0	742	25	160010	10	160000	10	160000	50	1280000	1	1	160020	0	160039	160039	139986	0	3	140019	160010	20	160000	20	480000	160039	160039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	246	0	0	10046	3	2	2	4	16	2	1	1	5	3	3	160034	15	13	160000	10	160040	160040	160040	160040	160040
160024	160039	1199	0	72	62	25	160010	11	160024	10	160000	60	1280000	1	1	160020	0	160039	160039	139986	0	3	140019	160010	20	160040	20	480000	160039	160214	1	1	160021	10	9	10	10	160000	10	0	2	1	0	249	0	0	10025	3	1	1	3	16	2	1	1	3	9	3	160034	15	13	160000	10	160040	160040	160040	160040	160040
160024	160039	1201	0	0	77	25	160010	10	160000	10	160000	50	1280000	1	1	160020	0	160039	160039	139986	0	3	140019	160010	20	160000	20	480000	160039	160039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	9	0	0	10027	3	2	1	9	16	2	2	1	3	9	3	160034	30	13	160000	10	160040	160040	160040	160040	160087

SHA256SU1

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations