Firestorm: SHA512H measurements

Code:

  sha512h q0, q1, v2.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2038	15	0	0	0	0	0	0	61	937	25	1000	1000	1000	68984	2019	2038	2038	1788	3	1896	1000	1000	3000	2038	2038	1	1	1001	1000	0	0	0	0	0	0	0	73	1	16	1	1	1970	1000	2039	2039	2039	2039	2039
1004	2038	15	0	0	0	0	0	0	61	937	25	1000	1000	1000	68984	2019	2038	2038	1788	3	1896	1000	1000	3000	2038	2038	1	1	1001	1000	0	0	0	0	0	0	0	73	1	16	1	1	1970	1000	2039	2039	2039	2039	2039
1004	2038	15	0	0	0	0	0	0	61	937	25	1000	1000	1000	68984	2019	2038	2038	1788	3	1896	1000	1000	3000	2038	2038	1	1	1001	1000	0	0	0	0	0	0	0	73	1	16	1	1	1970	1000	2039	2039	2039	2039	2039
1004	2038	16	0	0	0	0	0	0	61	937	25	1000	1000	1000	68984	2019	2038	2038	1788	3	1896	1000	1000	3000	2038	2038	1	1	1001	1000	0	0	0	1	0	0	0	73	1	16	1	1	1970	1000	2039	2039	2039	2039	2039
1004	2038	16	0	0	0	0	0	0	61	937	25	1000	1000	1000	68984	2019	2038	2038	1788	3	1896	1000	1000	3000	2038	2038	1	1	1001	1000	0	0	0	0	0	0	0	73	1	16	1	1	1970	1000	2039	2039	2039	2039	2039
1004	2038	15	0	0	0	0	0	0	61	937	25	1000	1000	1000	68984	2019	2038	2038	1788	3	1896	1000	1000	3000	2038	2038	1	1	1001	1000	0	0	0	0	0	0	0	73	1	16	1	1	1970	1000	2039	2039	2039	2039	2039
1004	2038	15	0	0	0	0	0	0	61	937	25	1000	1000	1000	68984	2019	2038	2038	1788	3	1896	1000	1000	3000	2038	2038	1	1	1001	1000	0	0	0	0	0	0	0	73	1	16	1	1	1970	1000	2039	2039	2039	2039	2039
1004	2038	15	0	0	0	0	0	0	61	937	25	1000	1000	1000	68984	2019	2038	2038	1788	3	1896	1000	1000	3000	2038	2038	1	1	1001	1000	0	0	0	3	0	0	0	73	1	16	1	1	1970	1000	2039	2039	2039	2039	2039
1004	2038	15	0	0	0	0	0	0	61	937	25	1000	1000	1000	68984	2019	2038	2038	1788	3	1896	1000	1000	3000	2038	2038	1	1	1001	1000	0	0	0	0	0	0	0	73	1	16	1	1	1970	1000	2039	2039	2039	2039	2039
1004	2038	15	0	0	0	0	0	0	61	937	25	1000	1000	1000	68984	2019	2038	2038	1788	3	1896	1000	1000	3000	2038	2038	1	1	1001	1000	0	0	0	17	0	0	0	73	1	16	1	1	1970	1000	2039	2039	2039	2039	2039

Test 2: Latency 1->1

Code:

  sha512h q0, q1, v2.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20038	150	0	0	0	9	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	0	20019	20038	20038	18638	3	18746	10100	200	10000	200	30000	20038	20038	1	1	10201	100	99	100	100	10000	100	0	0	0	0	712	1	2	16	2	2	19969	10000	100	20039	20039	20039	20039	20039
10204	20038	150	0	0	0	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	0	20019	20038	20038	18638	3	18746	10100	200	10000	200	30000	20038	20038	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	19969	10000	100	20039	20039	20039	20039	20039
10204	20038	150	0	0	0	33	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	0	20019	20038	20038	18638	3	18777	10100	200	10000	200	30000	20038	20038	1	1	10201	100	99	100	100	10000	100	0	0	1	3	710	1	2	16	2	2	19969	10000	100	20039	20039	20039	20039	20039
10204	20038	150	0	0	0	36	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	0	20019	20038	20038	18638	3	18746	10100	200	10000	200	30000	20038	20038	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	19969	10000	100	20039	20039	20039	20039	20039
10204	20038	150	0	0	0	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	0	20019	20038	20038	18638	3	18746	10100	200	10000	200	30000	20038	20038	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	19969	10000	100	20039	20039	20039	20039	20039
10204	20038	150	0	0	0	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	0	20019	20038	20038	18638	3	18746	10100	200	10000	200	30000	20038	20038	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	19969	10000	100	20039	20039	20039	20039	20039
10204	20038	150	0	0	0	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	0	20019	20038	20038	18638	3	18746	10100	200	10000	200	30000	20038	20038	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	19969	10000	100	20039	20039	20039	20039	20039
10204	20038	150	0	0	0	24	88	0	61	9937	25	10100	100	10000	100	10000	500	707984	0	20019	20038	20038	18638	3	18746	10100	200	10000	200	30000	20038	20038	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	19969	10000	100	20039	20039	20039	20039	20039
10204	20038	150	0	0	0	3	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	0	20019	20038	20038	18638	3	18746	10100	200	10000	200	30000	20038	20038	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	19969	10000	100	20039	20039	20039	20039	20039
10204	20038	150	0	0	0	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	0	20019	20038	20038	18638	3	18746	10100	200	10000	200	30000	20038	20038	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	2	16	2	2	19969	10000	100	20039	20039	20039	20039	20039

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20038	150	0	0	48	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20019	20038	20038	18660	3	18768	10010	20	10000	20	30000	20038	20038	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	19969	10000	10	20039	20039	20039	20039	20039
10024	20038	150	0	0	3	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20019	20038	20038	18660	3	18768	10010	20	10000	20	30000	20038	20038	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	19969	10000	10	20039	20039	20039	20039	20039
10024	20038	150	0	0	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	0	20019	20038	20038	18660	3	18768	10010	20	10000	20	30000	20038	20038	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	19969	10000	10	20039	20039	20039	20039	20039
10024	20038	150	0	0	0	0	158	9937	25	10010	10	10000	10	10000	50	707984	1	20019	20038	20038	18660	3	18768	10010	20	10000	20	30000	20038	20038	1	1	10021	10	9	10	10	10000	10	0	0	0	2	0	935	0	640	3	16	3	3	19969	10000	10	20039	20039	20039	20039	20039
10024	20038	150	0	0	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	0	20019	20038	20038	18660	3	18768	10010	20	10000	20	30000	20038	20038	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	19969	10000	10	20039	20039	20039	20039	20039
10024	20038	150	0	0	0	0	493	9937	25	10010	10	10000	10	10000	50	707984	1	20019	20038	20038	18660	3	18768	10010	20	10000	20	30000	20038	20038	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	19969	10000	10	20039	20039	20039	20039	20039
10024	20038	150	0	0	6	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20019	20038	20038	18660	3	18768	10010	20	10000	20	30000	20038	20038	1	1	10021	10	9	10	10	10000	10	0	0	0	1	0	0	0	640	3	16	3	4	19969	10000	10	20039	20039	20039	20039	20039
10024	20038	150	0	0	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20019	20038	20038	18660	3	18768	10010	20	10000	20	30000	20038	20038	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	19969	10000	10	20039	20039	20039	20039	20039
10024	20038	150	0	0	9	352	61	9937	25	10010	10	10000	10	10000	50	707984	1	20019	20038	20038	18660	3	18768	10010	20	10059	22	30000	20038	20038	1	1	10021	10	9	10	10	10000	10	2	0	0	1	0	0	2	671	3	16	3	3	20007	10000	10	20039	20039	20039	20039	20039
10024	20038	150	0	0	39	0	390	9899	25	10010	10	10000	10	10000	50	707984	1	20019	20038	20038	18660	3	18768	10010	20	10000	20	30000	20038	20038	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	3	3	19969	10000	10	20039	20039	20039	20039	20039

Test 3: Latency 1->2

Code:

  sha512h q0, q0, v1.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	18	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	0	61	19901	25	10100	100	10000	100	10000	500	1067500	0	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	710	2	16	2	2	29920	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	122	19901	25	10100	100	10000	100	10000	500	1067500	0	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	710	2	16	2	2	29920	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	19901	25	10100	100	10000	100	10000	500	1067500	1	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	710	2	16	2	2	29920	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	19901	25	10100	100	10000	100	10000	500	1067500	1	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	710	2	16	2	2	29920	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	24	61	19901	25	10100	100	10000	100	10000	500	1067500	0	30054	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	710	2	16	2	2	29920	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	21	61	19901	25	10100	100	10000	100	10000	500	1067500	1	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	710	2	16	2	2	29920	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	19901	25	10100	100	10000	100	10000	500	1067500	1	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	710	2	16	2	2	29920	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	19901	25	10100	100	10000	100	10000	500	1067500	0	30022	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	710	2	16	2	2	29920	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	61	19901	25	10100	100	10000	100	10000	620	1067500	0	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	710	2	16	2	2	29920	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	6	441	19901	25	10100	100	10000	100	10000	500	1067500	0	30018	30037	30037	28589	3	28745	10100	202	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	740	2	16	2	2	29920	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	0	318	0	0	61	19901	25	10010	10	10000	10	10000	50	1067500	1	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	3	16	2	2	29920	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	15	0	0	61	19901	25	10010	10	10000	10	10000	50	1067500	1	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29920	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	19901	25	10010	10	10000	10	10000	50	1067500	1	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29920	0	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	0	0	0	0	0	61	19901	25	10010	10	10000	10	10000	50	1067500	1	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29920	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	19901	25	10010	10	10000	10	10000	50	1067500	1	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29920	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	19901	25	10010	10	10000	10	10000	50	1067500	1	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29920	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	19901	25	10010	10	10000	10	10000	50	1067500	1	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29920	0	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	0	0	0	0	0	61	19901	25	10010	10	10000	10	10000	50	1067500	1	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29920	0	10000	10	30038	30038	30038	30038	30038
10024	30084	224	0	0	0	0	0	0	0	61	19901	25	10015	10	10000	10	10000	50	1067500	1	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29920	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	61	19901	25	10010	10	10000	10	10000	50	1067500	1	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29920	0	10000	10	30038	30038	30038	30038	30038

Test 4: Latency 1->3

Code:

  sha512h q0, q1, v0.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30084	225	0	0	0	0	0	3	0	0	445	19901	25	10100	100	10000	100	10000	500	1067500	0	30018	30226	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	2	0	0	0	0	0	710	1	16	1	1	29920	0	10000	100	30038	30038	30038	30225	30038
10204	30037	225	0	1	0	0	0	0	0	0	469	19901	25	10100	100	10000	100	10000	500	1067500	1	30018	30037	30037	28589	3	28745	10145	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	3	0	0	0	710	1	16	1	1	29920	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	21	0	0	61	19901	25	10100	100	10000	100	10000	500	1067500	0	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	2	0	6	0	0	0	710	1	16	1	1	29920	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	30	0	0	61	19901	25	10100	100	10000	100	10000	500	1067500	0	30018	30037	30037	28606	3	28745	10100	200	10000	200	30000	30037	30085	1	1	10201	100	99	100	100	10000	100	0	0	0	1	0	9	0	0	0	710	1	16	1	1	29920	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	0	0	9	0	0	145	19901	25	10100	100	10000	100	10000	500	1067500	0	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	3	0	0	0	0	0	710	1	16	1	1	29920	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	24	0	0	124	19901	25	10100	100	10008	100	10000	500	1067500	0	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29920	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	3	0	0	61	19901	25	10100	100	10000	100	10000	550	1067500	0	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29920	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	19901	25	10100	100	10000	100	10000	500	1067500	0	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29920	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	61	19901	25	10100	100	10000	100	10000	500	1067500	0	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29920	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	0	84	19901	25	10100	100	10000	100	10000	500	1067500	0	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	3	0	0	0	710	1	16	1	1	29920	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	0	0	0	61	19901	25	10010	10	10000	10	10000	50	1067500	0	30018	0	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	4	3	29920	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	0	0	0	0	61	19901	25	10010	10	10000	10	10000	50	1067500	0	30018	0	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	4	16	4	3	29920	10000	10	30038	30229	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	19901	25	10010	10	10000	10	10000	50	1067500	1	30018	0	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	4	29920	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	19901	25	10010	10	10000	10	10000	50	1067500	0	30018	0	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	4	4	29920	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	19901	25	10010	10	10000	10	10000	50	1067500	0	30018	0	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	4	29920	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	19901	25	10010	10	10000	10	10000	50	1067500	1	30018	0	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	4	16	3	4	29920	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	19901	25	10010	10	10000	10	10000	50	1067500	0	30018	0	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	4	29920	10000	10	30038	30227	30085	30038	30038
10024	30037	225	0	0	0	0	0	0	61	19901	25	10010	10	10000	10	10000	50	1067500	0	30018	0	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	4	16	4	4	29920	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	19901	25	10010	10	10000	10	10000	50	1067500	0	30018	0	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	4	16	3	4	29920	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	19901	25	10010	10	10000	10	10000	50	1067500	1	30018	0	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	640	4	16	4	4	29920	10000	10	30038	30038	30038	30038	30038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  sha512h q0, q8, v9.2d
  movi v1.16b, 0
  sha512h q1, q8, v9.2d
  movi v2.16b, 0
  sha512h q2, q8, v9.2d
  movi v3.16b, 0
  sha512h q3, q8, v9.2d
  movi v4.16b, 0
  sha512h q4, q8, v9.2d
  movi v5.16b, 0
  sha512h q5, q8, v9.2d
  movi v6.16b, 0
  sha512h q6, q8, v9.2d
  movi v7.16b, 0
  sha512h q7, q8, v9.2d

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	160038	1199	0	0	0	0	978	352	61	79937	49	80100	100	80000	100	80000	500	5677984	0	160019	0	160038	160038	139907	3	139996	80100	200	80000	200	240000	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	0	10110	1	16	1	1	159981	0	160000	100	160039	160039	160039	160039	160039
160204	160038	1199	0	0	0	0	1191	0	61	79937	25	80100	100	80000	100	80000	500	5677984	0	160019	0	160038	160038	139888	33	139996	80100	200	80000	200	240000	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	0	10135	1	16	1	1	159981	0	160000	100	160039	160039	160039	160039	160039
160204	160038	1199	0	0	0	0	465	0	61	79937	25	80100	100	80000	100	80000	500	5677984	0	160019	0	160038	160038	139888	3	139996	80100	200	80000	200	240000	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	11	0	0	0	0	0	10110	1	16	1	1	159981	0	160000	100	160039	160039	160039	160039	160039
160204	160038	1199	0	0	0	0	1149	0	943	79937	25	80100	100	80000	100	80000	500	5677984	0	160019	0	160038	160038	139888	3	139996	80100	200	80000	200	240000	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	0	10110	1	16	1	1	159981	0	160000	100	160039	160039	160039	160039	160039
160204	160038	1199	0	0	0	0	1074	0	726	79937	25	80100	100	80000	100	80000	500	5677984	0	160019	0	160038	160038	139888	3	139996	80100	200	80000	200	240000	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	0	10110	1	16	1	1	159981	0	160000	100	160039	160039	160039	160039	160039
160204	160038	1198	0	0	0	0	1206	0	61	79937	25	80100	100	80000	100	80000	500	5677984	0	160019	0	160038	160038	139888	3	139996	80100	200	80000	200	240000	160038	160038	1	1	160202	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	0	10110	1	16	1	1	159981	0	160000	100	160039	160039	160039	160039	160039
160204	160038	1199	0	0	0	0	417	0	61	79937	25	80100	100	80000	100	80000	500	5677984	0	160019	0	160038	160038	139888	3	139996	80100	200	80000	200	240000	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	0	10110	1	16	1	1	159981	0	160000	100	160039	160039	160099	160039	160039
160204	160038	1199	0	0	0	0	471	0	61	79937	25	80112	100	80000	100	80000	500	5677984	0	160019	0	160038	160038	139888	3	139996	80100	200	80000	200	240000	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	1	10110	1	16	1	1	159981	11	160000	100	160039	160039	160039	160039	160039
160204	160038	1198	0	0	0	0	1329	0	61	79937	25	80100	100	80000	100	80000	500	5677984	0	160019	0	160038	160038	139888	3	139996	80100	200	80000	200	240000	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	0	10110	1	16	1	1	159981	0	160000	100	160039	160039	160039	160039	160039
160204	160038	1198	0	0	0	0	1101	0	61	79937	25	80100	100	80000	100	80000	500	5677984	0	160019	0	160038	160038	139888	3	139996	80100	200	80000	200	240000	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	0	0	0	0	0	10110	1	16	1	1	159981	0	160000	100	160279	160039	160039	160039	160135

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	160038	1198	0	0	0	0	6	0	0	73	79937	25	80010	10	80000	10	80000	50	5677984	0	1	160019	160038	160038	139910	3	140018	80056	20	80000	20	240186	160038	160038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	6	2	2	5	16	2	1	1	6	4	159983	0	20	17	18	160000	10	160039	160039	160039	160039	160039
160024	160038	1199	0	0	0	0	0	0	0	67	79937	25	80010	10	80000	10	80000	50	5677984	1	0	160019	160038	160038	139910	3	140018	80010	20	80000	20	240000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	6	1	1	2	16	2	1	1	4	2	159983	0	20	34	18	160000	10	160039	160039	160039	160039	160039
160025	160038	1199	0	0	0	0	0	0	0	257	79937	25	80010	10	80000	10	80000	50	5677984	1	1	160019	160038	160038	139910	3	140018	80010	20	80000	20	240000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	1	10078	3	1	1	4	24	2	1	1	2	4	159983	2	20	17	9	160000	10	160039	160039	160039	160039	160039
160024	160086	1200	1	0	0	0	0	0	0	88	79937	25	80010	10	80000	10	80000	50	5677984	1	1	160019	160038	160038	139910	3	140018	80010	20	80000	20	240000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	3	1	1	6	16	2	1	1	3	6	159983	0	20	17	9	160000	10	160039	160039	160039	160039	160039
160024	160038	1199	0	0	0	0	21	0	0	67	79937	25	80010	10	80000	10	80000	50	5677984	1	1	160019	160038	160038	139910	3	140018	80010	20	80000	20	240000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	3	1	1	4	16	2	1	1	4	2	159983	0	20	17	9	160000	10	160039	160039	160039	160039	160039
160024	160038	1199	1	0	0	0	18	0	0	67	79937	25	80010	10	80000	10	80000	50	5677984	1	1	160019	160038	160038	139910	3	140018	80010	20	80000	20	240000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	3	1	1	2	16	2	2	1	4	2	159983	0	20	17	9	160000	10	160039	160039	160039	160039	160039
160024	160038	1199	0	0	0	0	0	0	0	67	79937	25	80010	10	80000	10	80000	50	5677984	1	1	160019	160038	160038	139910	3	140018	80010	20	80000	20	240000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	2	0	0	2	10022	3	1	1	6	24	2	1	1	2	4	160018	0	20	17	9	160000	10	160039	160039	160039	160039	160039
160024	160038	1199	0	0	0	0	12	0	0	765	79937	25	80010	10	80000	10	80000	50	5677984	1	1	160019	160038	160038	139910	3	140018	80010	20	80000	20	240000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	0	2	1	1	0	941	0	10022	3	1	1	4	16	2	1	1	4	6	159983	0	20	17	9	160000	10	160039	160039	160039	160039	160039
160024	160038	1199	0	0	0	0	0	0	0	67	79918	25	80010	10	80000	10	80000	50	5677984	1	1	160019	160038	160038	139910	3	140018	80010	20	80000	20	240000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	3	1	1	4	16	2	1	1	4	2	160049	0	20	17	9	160000	10	160039	160039	160039	160039	160039
160024	160038	1199	0	0	0	0	0	0	0	67	79937	25	80010	10	80000	10	80000	50	5677984	1	1	160019	160038	160038	139910	3	140018	80010	20	80062	20	240000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	3	1	1	2	16	2	1	1	2	4	159983	0	20	17	9	160000	10	160039	160039	160039	160039	160039

Test 6: throughput

Count: 16

Code:

  sha512h q0, q16, v17.2d
  sha512h q1, q16, v17.2d
  sha512h q2, q16, v17.2d
  sha512h q3, q16, v17.2d
  sha512h q4, q16, v17.2d
  sha512h q5, q16, v17.2d
  sha512h q6, q16, v17.2d
  sha512h q7, q16, v17.2d
  sha512h q8, q16, v17.2d
  sha512h q9, q16, v17.2d
  sha512h q10, q16, v17.2d
  sha512h q11, q16, v17.2d
  sha512h q12, q16, v17.2d
  sha512h q13, q16, v17.2d
  sha512h q14, q16, v17.2d
  sha512h q15, q16, v17.2d

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0002

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	09	l2 tlb miss instruction (0a)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	320038	2398	0	1	1	18	2428	159937	25	160100	100	160000	100	160000	500	11357984	0	320019	0	320038	320038	299888	0	3	299996	160100	200	160000	200	480000	320038	320038	1	1	160201	100	99	100	100	160000	100	0	12	0	0	0	0	10110	2	16	2	4	319969	160000	100	320039	320039	320039	320039	320039
160204	320038	2398	0	0	0	12	61	159937	25	160100	100	160000	100	160000	500	11357984	0	320019	0	320038	320038	299888	0	3	299996	160100	200	160000	200	480000	320038	320038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	10110	2	16	2	2	319969	160000	100	320039	320039	320039	320039	320039
160204	320038	2397	0	0	0	9	726	159937	25	160100	100	160000	100	160000	500	11357984	0	320019	0	320038	320038	299888	0	3	299996	160100	200	160000	200	480000	320038	320038	1	1	160201	100	99	100	100	160000	100	0	0	0	3	0	0	10110	3	16	2	2	320043	160000	100	320039	320039	320039	320039	320039
160204	320038	2397	0	0	0	0	61	159937	25	160100	100	160000	117	160000	500	11357984	0	320019	0	320038	320420	299888	0	3	299996	160100	200	160286	202	480000	320038	320038	2	1	160201	100	99	100	100	160000	100	0	0	2	0	0	0	10110	2	16	2	2	319969	160000	100	320039	320039	320039	320039	320039
160204	320038	2398	0	0	0	0	726	159937	25	160100	100	160000	100	160000	500	11357984	0	320019	3	320038	320038	299888	0	3	299996	160100	200	160000	200	480000	320038	320038	1	1	160201	100	99	100	100	160000	100	0	0	0	12	0	0	10110	2	16	2	2	319969	160000	100	320039	320039	320039	320039	320039
160204	320038	2397	0	0	0	0	61	159937	25	160100	100	160000	100	160000	500	11357984	0	320019	0	320038	320038	299888	0	3	299996	160100	200	160000	200	480000	320038	320038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10132	2	16	2	2	319969	160000	100	320039	320039	320039	320039	320039
160204	320038	2398	0	0	0	0	726	159937	25	160100	100	160000	100	160000	500	11357984	1	320019	0	320038	320038	299888	0	3	299996	160100	200	160000	200	480000	320038	320038	1	1	160201	100	99	100	100	160000	100	0	0	0	6	0	0	10110	2	16	2	2	319969	160000	100	320087	320039	320039	320039	320039
160204	320038	2397	0	0	0	0	94	159937	25	160100	100	160000	100	160000	500	11357984	0	320019	0	320038	320038	299888	0	3	299996	160100	200	160000	200	480000	320038	320038	1	1	160202	100	99	100	100	160000	100	0	0	0	0	0	0	10110	2	16	2	2	320004	160000	100	320039	320039	320039	320039	320039
160204	320038	2398	0	0	0	0	726	159937	53	160100	100	160000	100	160000	500	11357984	1	320019	0	320038	320038	299888	0	3	299996	160100	200	160000	200	480000	320038	320038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	10110	2	16	2	2	319969	160000	100	320039	320039	320039	320039	320039
160205	320038	2397	0	0	0	0	61	159937	25	160100	100	160000	100	160000	500	11357984	0	320019	3	320038	320038	299888	0	3	300032	160100	200	160000	200	480000	320038	320038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	0	10110	2	16	2	2	319969	160000	100	320039	320039	320039	320039	320039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0002

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cd	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	320038	2398	0	0	0	0	0	0	0	0	0	0	67	159937	25	160010	10	160000	10	160000	50	11357984	1	1	0	320019	0	320038	320038	299910	0	3	300054	160010	20	160000	20	480000	320038	320038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10023	8	5	1	1	44	16	2	2	2	31	30	319969	0	21	38	20	160000	10	320039	320039	320039	320039	320039
160024	320038	2397	1	0	0	1	0	0	0	12	0	0	738	159937	25	160010	10	160000	10	160000	50	11357984	0	1	0	320019	0	320038	320038	299910	0	3	300018	160010	20	160000	20	480204	320038	320038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10024	16	2	2	0	31	16	2	2	2	19	30	319969	0	42	38	20	160000	10	320039	320039	320039	320039	320039
160024	320038	2397	0	0	0	0	0	0	0	0	0	0	116	159937	44	160010	10	160000	10	160000	50	11357984	0	1	10	320067	3	320038	320038	299910	0	3	300018	160010	20	160068	20	480000	320038	320038	2	1	160021	10	9	10	10	160000	10	0	0	0	0	18	0	0	0	10025	16	7	2	1	18	16	2	2	1	29	17	319969	0	21	38	20	160000	10	320039	320039	320039	320039	320039
160024	320038	2397	1	0	0	1	0	0	0	0	0	0	116	159937	25	160010	10	160000	10	160000	50	11357984	0	1	10	320019	0	320038	320038	299910	0	3	300018	160010	20	160000	20	480000	320038	320038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10025	6	8	2	1	20	16	2	2	2	31	21	319969	0	42	38	20	160000	10	320039	320039	320039	320039	320039
160024	320038	2397	1	0	0	1	0	0	0	0	0	0	738	159937	25	160010	10	160000	10	160000	50	11357984	1	1	10	320019	0	320038	320038	299910	0	3	300018	160010	20	160000	20	480000	320038	320038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	3	0	0	0	10025	16	2	2	1	16	16	2	2	2	29	17	319969	0	42	60	10	160000	10	320039	320039	320039	320039	320039
160024	320038	2397	1	0	0	1	0	0	0	0	0	0	116	159937	25	160010	10	160012	10	160000	50	11357984	1	1	10	320019	0	320038	320038	299910	0	3	300018	160010	20	160000	20	480000	320038	320038	1	1	160021	10	9	10	10	160000	10	0	0	1	0	0	0	0	0	10023	13	5	1	1	25	16	1	1	1	27	18	319969	0	21	19	10	160000	10	320039	320039	320039	320039	320039
160024	320038	2398	1	0	0	1	0	0	0	0	0	0	116	159937	25	160010	10	160000	10	160000	55	11357984	1	1	10	320019	0	320038	320038	299910	0	3	300018	160010	20	160000	20	480000	320038	320038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10023	13	1	1	1	40	16	1	1	1	21	26	320017	0	21	19	10	160000	10	320086	320039	320039	320039	320039
160024	320038	2397	1	0	0	1	0	0	0	0	0	0	116	159937	25	160010	10	160000	10	160000	50	11357984	1	1	10	320019	0	320038	320038	299910	0	3	300018	160057	20	160000	20	480000	320038	320038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10023	13	1	1	1	27	16	1	1	1	28	28	319969	0	21	19	10	160000	10	320039	320039	320039	320039	320039
160024	320087	2398	1	0	0	1	0	0	0	0	0	0	116	159937	25	160010	10	160000	10	160000	50	11357984	0	1	0	320019	0	320038	320038	299910	0	3	300018	160010	20	160000	20	480000	320038	320038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	1	0	10023	13	1	1	1	27	16	1	1	1	18	27	320017	0	21	19	10	160000	10	320039	320039	320039	320039	320039
160024	320038	2397	1	0	0	1	0	0	0	0	0	0	781	159937	25	160010	10	160000	10	160000	50	11357984	1	1	10	320019	0	320086	320038	299910	0	3	300018	160010	20	160000	20	480000	320038	320038	1	1	160021	10	9	10	10	160000	10	0	0	1	0	0	0	0	0	10023	13	1	1	1	19	16	1	1	1	28	19	319969	0	21	19	10	160000	10	320039	320039	320039	320039	320039

SHA512H

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations