Firestorm: SHA512H2 measurements

Code:

  sha512h2 q0, q1, v2.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2038	15	0	1	64	937	25	1000	1000	1000	68984	0	2019	2038	2038	1788	3	1896	1000	1000	3000	2038	2038	1	1	1001	1000	0	0	0	75	6	16	6	5	1970	1000	2039	2039	2039	2039	2039
1004	2038	15	0	1	61	937	25	1000	1000	1000	68984	1	2019	2038	2038	1788	3	1896	1000	1000	3000	2038	2038	1	1	1001	1000	0	0	0	75	6	16	6	6	1970	1000	2039	2039	2039	2039	2039
1004	2038	15	0	1	61	937	25	1000	1000	1000	68984	1	2019	2038	2038	1788	3	1896	1000	1000	3000	2038	2038	1	1	1001	1000	0	0	0	75	6	16	6	6	1970	1000	2039	2039	2039	2039	2039
1004	2038	15	0	1	61	937	25	1000	1000	1000	68984	1	2019	2038	2038	1788	3	1896	1000	1000	3000	2038	2038	1	1	1001	1000	0	0	0	75	6	16	5	5	1970	1000	2039	2039	2039	2039	2039
1004	2038	15	0	1	61	937	25	1000	1000	1000	68984	1	2019	2038	2038	1788	3	1896	1000	1000	3000	2038	2038	1	1	1001	1000	0	0	0	75	7	16	5	6	1970	1000	2039	2039	2039	2039	2039
1004	2038	16	0	1	61	937	25	1000	1000	1000	68984	0	2019	2038	2038	1788	3	1896	1000	1000	3000	2038	2038	1	1	1001	1000	0	0	0	75	6	16	6	6	1970	1000	2039	2039	2039	2039	2039
1004	2038	15	0	1	61	937	25	1000	1000	1000	68984	0	2019	2038	2038	1788	3	1896	1000	1000	3000	2038	2038	1	1	1001	1000	0	0	0	75	5	16	7	7	1970	1000	2039	2039	2039	2039	2039
1004	2038	16	0	1	61	937	25	1000	1000	1000	68984	1	2019	2038	2038	1788	3	1896	1000	1000	3000	2038	2038	1	1	1001	1000	0	0	0	75	6	16	6	6	1970	1000	2039	2039	2039	2039	2039
1004	2038	15	0	2	61	937	25	1000	1000	1000	68984	1	2019	2038	2038	1788	3	1896	1000	1000	3000	2038	2038	1	1	1001	1000	0	1	0	75	5	16	6	6	1970	1000	2039	2039	2039	2039	2039
1004	2038	15	0	1	61	937	25	1000	1000	1000	68984	1	2019	2038	2038	1788	3	1896	1000	1000	3000	2038	2038	1	1	1001	1000	0	0	0	75	5	16	5	5	1970	1000	2039	2039	2039	2039	2039

Test 2: Latency 1->1

Code:

  sha512h2 q0, q1, v2.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20038	150	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	0	20019	20038	20038	18638	3	18746	10100	200	10000	200	30000	20038	20038	1	1	10201	100	99	100	100	10000	100	0	0	710	1	3	16	3	3	19969	10000	100	20039	20039	20039	20039	20039
10204	20038	150	1	33	0	61	9937	25	10100	100	10000	100	10000	500	707984	0	20019	20038	20038	18638	3	18746	10100	200	10000	200	30000	20038	20038	1	1	10201	100	99	100	100	10000	100	0	0	710	1	3	16	3	3	19969	10000	100	20039	20039	20039	20039	20039
10204	20038	150	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	1	20019	20038	20038	18638	3	18746	10100	200	10000	200	30000	20038	20038	1	1	10201	100	99	100	100	10000	100	0	0	710	1	3	16	3	3	19969	10000	100	20039	20039	20039	20039	20039
10204	20038	150	0	39	0	61	9937	25	10100	100	10000	100	10000	500	707984	0	20019	20038	20038	18638	3	18746	10100	200	10000	200	30000	20038	20038	1	1	10201	100	99	100	100	10000	100	0	0	710	1	3	16	3	3	19969	10000	100	20039	20039	20039	20039	20039
10204	20038	150	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	0	20019	20038	20038	18638	3	18746	10100	200	10000	200	30000	20038	20038	1	1	10201	100	99	100	100	10000	100	0	0	710	1	3	16	3	3	19969	10000	100	20039	20039	20039	20039	20039
10204	20038	150	0	6	0	61	9937	25	10100	100	10000	100	10000	500	707984	0	20019	20038	20038	18638	3	18746	10100	200	10000	200	30000	20038	20038	1	1	10201	100	99	100	100	10000	100	0	0	710	1	4	16	3	3	19969	10000	100	20039	20039	20039	20039	20039
10204	20038	150	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	1	20019	20038	20038	18638	3	18746	10100	200	10000	200	30000	20038	20038	1	1	10201	100	99	100	100	10000	100	0	0	710	1	3	16	3	3	19969	10000	100	20039	20039	20039	20039	20039
10204	20038	150	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	0	20019	20038	20038	18638	3	18746	10100	200	10000	200	30000	20038	20038	1	1	10201	100	99	100	100	10000	100	0	0	710	1	3	16	3	3	19969	10000	100	20039	20039	20039	20039	20039
10204	20038	150	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	0	20019	20038	20038	18638	3	18746	10100	200	10000	200	30000	20038	20038	1	1	10201	100	99	100	100	10000	100	0	0	710	1	3	16	3	3	19969	10000	100	20039	20039	20039	20039	20039
10204	20038	150	0	0	0	61	9937	25	10100	100	10012	100	10000	500	707984	0	20019	20038	20038	18638	3	18746	10100	200	10000	200	30000	20038	20038	1	1	10201	100	99	100	100	10000	100	0	0	710	1	3	16	3	3	19969	10000	100	20039	20039	20039	20039	20039

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20038	150	15	61	9937	25	10010	10	10000	10	10000	50	707984	1	20019	20038	20038	18660	3	18768	10010	20	10000	20	30000	20038	20038	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	19969	10000	10	20039	20039	20039	20039	20039
10024	20038	150	30	61	9918	25	10022	10	10000	10	10000	50	707984	1	20019	20038	20038	18660	3	18768	10010	20	10000	20	30000	20038	20038	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19969	10000	10	20039	20039	20039	20039	20039
10024	20038	150	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20019	20038	20038	18660	3	18768	10010	20	10000	20	30000	20038	20038	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	3	3	19969	10000	10	20039	20039	20039	20039	20039
10024	20038	150	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20019	20038	20038	18660	3	18768	10010	20	10000	20	30000	20038	20038	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	19969	10000	10	20039	20039	20039	20039	20039
10024	20038	150	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20019	20038	20038	18660	3	18768	10010	20	10000	20	30000	20038	20038	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19969	10000	10	20039	20039	20039	20039	20039
10024	20038	150	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20019	20038	20038	18660	3	18768	10010	20	10000	20	30000	20038	20038	1	1	10021	10	9	10	10	10000	10	0	0	4	0	640	2	16	3	3	19969	10000	10	20039	20039	20039	20039	20039
10024	20038	150	27	61	9937	25	10010	10	10000	10	10000	50	707984	1	20019	20038	20038	18660	3	18768	10010	20	10000	20	30000	20038	20038	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	19969	10000	10	20039	20039	20039	20039	20039
10024	20038	150	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20019	20038	20061	18660	3	18768	10010	20	10000	20	30000	20038	20038	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	3	3	19969	10000	10	20039	20039	20039	20039	20039
10024	20038	150	3	61	9937	25	10010	10	10000	10	10000	50	707984	1	20019	20038	20038	18660	3	18768	10010	20	10000	20	30000	20038	20038	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19969	10000	10	20039	20039	20039	20039	20039
10024	20038	150	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20019	20038	20038	18660	3	18768	10010	20	10000	20	30000	20038	20038	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	3	2	19969	10000	10	20039	20039	20039	20039	20039

Test 3: Latency 1->2

Code:

  sha512h2 q0, q0, v1.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	224	61	19901	25	10100	100	10000	100	10000	500	1067500	0	30018	30037	30037	28589	0	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	2	16	2	2	29920	10000	100	30038	30038	30038	30038	30038
10204	30037	225	61	19901	25	10100	100	10007	100	10000	500	1067500	0	30018	30037	30037	28589	0	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	2	16	2	2	29920	10000	100	30038	30038	30038	30038	30038
10204	30037	224	61	19901	25	10100	100	10000	100	10000	500	1067500	0	30018	30037	30037	28589	0	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	2	16	2	2	29920	10000	100	30038	30038	30038	30038	30038
10204	30037	224	61	19901	25	10100	100	10000	100	10000	500	1067500	0	30018	30037	30037	28589	0	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	2	16	2	2	29920	10000	100	30038	30038	30038	30038	30038
10204	30037	225	61	19901	25	10100	100	10000	100	10000	500	1067500	0	30018	30037	30037	28589	0	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	2	16	2	2	29920	10000	100	30038	30038	30038	30038	30038
10204	30037	224	61	19901	25	10100	100	10000	100	10000	500	1067500	0	30018	30037	30037	28589	0	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	2	16	2	2	29920	10000	100	30038	30038	30038	30038	30038
10204	30037	224	61	19901	25	10100	100	10000	100	10000	500	1067500	0	30018	30037	30037	28589	0	3	28745	10100	200	10000	200	30000	30084	30037	1	1	10201	100	99	100	100	10000	100	1	0	710	2	16	2	2	29920	10000	100	30038	30038	30038	30038	30038
10204	30037	225	61	19901	25	10100	100	10000	100	10000	500	1067500	0	30018	30037	30037	28589	0	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	2	16	2	2	29920	10000	100	30038	30038	30038	30038	30038
10204	30037	225	61	19901	25	10100	100	10000	100	10000	500	1067500	0	30018	30037	30037	28589	0	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	2	16	2	2	29920	10000	100	30038	30038	30038	30038	30038
10204	30037	225	61	19901	25	10100	100	10000	100	10000	500	1067500	0	30018	30037	30037	28589	0	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	2	16	2	2	29920	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	0	0	61	19901	25	10010	10	10000	10	10000	50	1067500	30018	0	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29920	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	19901	25	10010	10	10000	10	10000	50	1067500	30018	0	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29920	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	19901	25	10010	10	10000	10	10000	50	1067500	30018	0	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	3	0	640	2	16	2	2	29920	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	19901	25	10010	10	10000	10	10000	50	1067500	30018	0	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29920	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	19901	25	10010	10	10000	10	10000	50	1067500	30018	0	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29920	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	19901	25	10010	10	10000	10	10000	50	1067500	30018	0	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29920	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	19901	25	10010	10	10000	10	10000	50	1067500	30018	0	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29920	0	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	0	0	0	61	19901	25	10010	10	10000	10	10000	50	1067500	30018	0	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	3	1	0	0	0	640	2	16	2	2	29920	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	19901	25	10010	10	10000	10	10000	50	1067500	30018	0	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29920	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	61	19901	25	10010	10	10000	10	10000	50	1067500	30018	0	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29920	0	10000	10	30038	30038	30038	30038	30038

Test 4: Latency 1->3

Code:

  sha512h2 q0, q1, v0.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	61	19901	25	10100	100	10000	100	10000	500	1067500	1	0	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	2	1	16	1	1	29920	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	61	19901	25	10100	100	10000	100	10000	500	1067500	1	0	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	2	1	16	1	1	29920	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	19901	25	10100	100	10000	100	10000	500	1067500	0	2	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	2	1	16	1	1	29920	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	19901	25	10100	100	10000	100	10000	500	1067500	1	0	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	0	1	16	1	1	29920	0	10000	100	30086	30038	30038	30038	30038
10204	30037	225	0	612	19901	25	10100	100	10000	100	10000	500	1067500	1	0	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	0	1	16	1	1	29920	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	9	61	19901	25	10100	100	10000	100	10000	500	1067500	1	0	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	0	1	16	1	1	29920	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	19901	25	10100	100	10000	100	10000	500	1067500	0	0	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	3	0	0	710	2	1	16	1	1	29920	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	19901	25	10100	100	10000	100	10000	500	1067500	1	0	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	2	1	16	1	1	29920	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	6	61	19901	25	10100	100	10000	100	10000	500	1067500	0	2	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	0	1	16	1	1	29920	0	10000	100	30038	30038	30038	30038	30085
10204	30037	225	0	61	19901	25	10100	100	10000	100	10000	500	1067500	0	0	30018	30037	30037	28589	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	710	2	1	16	1	1	29920	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	2	129	19901	25	10010	10	10000	10	10000	50	1067500	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	643	8	16	10	10	29920	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	2	234	19901	25	10010	10	10000	10	10000	50	1067500	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	643	10	16	10	10	29920	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	2	104	19901	25	10010	10	10000	10	10000	50	1067500	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	643	10	16	6	10	29920	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	2	1294	19901	25	10010	10	10000	10	10000	50	1067500	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	643	11	16	11	11	29920	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	2	192	19901	25	10010	10	10000	10	10000	50	1067500	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	643	10	16	10	5	29920	10000	10	30038	30038	30086	30038	30038
10024	30037	225	0	0	2	85	19901	25	10010	10	10000	10	10000	50	1067500	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	643	10	16	10	10	29920	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	2	192	19901	25	10010	10	10000	10	10000	50	1067500	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	643	10	16	10	10	29920	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	2	213	19901	25	10010	10	10000	10	10000	50	1067500	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	643	10	16	10	10	29920	10000	10	30038	30038	30038	30038	30038
10024	30037	225	30	0	2	1004	19901	25	10010	10	10000	10	10000	50	1067500	30018	30037	30037	28611	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	643	10	16	11	5	29920	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	2	150	19901	25	10010	10	10000	10	10000	50	1067500	30018	30037	30037	28648	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	643	8	16	8	8	29920	10000	10	30086	30038	30038	30038	30038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  sha512h2 q0, q8, v9.2d
  movi v1.16b, 0
  sha512h2 q1, q8, v9.2d
  movi v2.16b, 0
  sha512h2 q2, q8, v9.2d
  movi v3.16b, 0
  sha512h2 q3, q8, v9.2d
  movi v4.16b, 0
  sha512h2 q4, q8, v9.2d
  movi v5.16b, 0
  sha512h2 q5, q8, v9.2d
  movi v6.16b, 0
  sha512h2 q6, q8, v9.2d
  movi v7.16b, 0
  sha512h2 q7, q8, v9.2d

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	160038	1198	0	0	0	9	0	61	79937	25	80100	100	80000	100	80000	500	5677984	0	160019	0	160038	160038	139888	3	139996	80100	200	80000	200	240000	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	2	0	0	0	0	0	10110	9	16	8	4	159981	160000	100	160039	160039	160039	160039	160039
160204	160038	1198	0	0	0	0	0	244	79937	25	80100	100	80000	100	80000	500	5677984	1	160019	0	160038	160038	139888	3	139996	80100	200	80000	200	240000	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10110	9	16	9	4	159981	160000	100	160039	160039	160039	160039	160039
160204	160038	1199	0	0	0	60	0	61	79937	25	80100	100	80000	100	80000	500	5677984	1	160019	0	160038	160038	139888	3	139996	80100	200	80000	200	240000	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10110	9	16	9	4	159981	160000	100	160039	160039	160039	160039	160039
160204	160038	1198	0	0	0	0	0	61	79937	25	80100	100	80000	100	80000	500	5677984	0	160019	3	160038	160038	139888	3	139996	80100	200	80000	200	240000	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10110	9	16	9	9	159981	160000	100	160039	160039	160039	160039	160039
160204	160038	1199	0	0	0	9	0	61	79937	25	80100	100	80000	100	80000	500	5677984	0	160019	0	160038	160038	139888	3	139996	80100	200	80000	200	240000	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	168	0	10110	9	16	10	10	159981	160000	100	160039	160039	160039	160039	160039
160204	160038	1198	0	0	0	0	0	726	79937	25	80100	100	80000	100	80000	500	5677984	0	160019	0	160038	160038	139888	3	139996	80100	200	80000	200	240000	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10110	9	16	8	8	159981	160000	100	160039	160039	160039	160039	160039
160204	160038	1199	0	0	0	0	0	2414	79937	25	80100	100	80000	100	80000	505	5677984	1	160019	0	160038	160038	139888	3	139996	80100	200	80000	200	240000	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10110	9	16	9	9	159981	160000	100	160039	160039	160039	160039	160039
160204	160038	1199	0	0	0	0	0	233	79937	25	80100	100	80000	100	80000	500	5677984	1	160019	0	160038	160038	139888	3	139996	80100	200	80000	200	240000	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10110	8	16	9	9	159981	160000	100	160039	160039	160039	160039	160039
160204	160038	1199	0	0	0	0	0	61	79937	25	80100	100	80000	100	80000	500	5677984	1	160019	0	160038	160038	139888	3	139996	80100	200	80000	200	240000	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	180	0	10110	4	16	9	10	159981	160000	100	160039	160039	160039	160039	160039
160204	160038	1198	0	0	0	0	0	61	79937	25	80100	100	80000	100	80000	500	5677984	0	160079	0	160038	160038	139888	3	139996	80100	200	80000	200	240000	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	0	0	0	10110	10	16	9	9	159981	160000	100	160039	160039	160039	160039	160039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	160038	1199	0	0	1	1	1	0	0	0	505	79937	25	80010	10	80000	10	80000	50	5677984	1	1	5	160056	0	160038	160038	139920	12	140018	80276	20	80226	20	240681	160087	160278	4	1	160021	10	9	10	10	160000	10	2	4	2	1	903	2	0	0	10022	8	1	1	23	16	2	1	1	16	44	159983	1	15	13	8	160000	10	160039	160039	160039	160086	160039
160024	160038	1285	0	0	0	0	0	0	0	0	73	79937	25	80010	10	80000	10	80000	50	5677984	0	1	0	160019	0	160038	160038	139910	3	140018	80010	20	80000	20	240000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	3	1	1	14	16	2	1	1	37	12	159983	0	15	13	8	160000	10	160039	160039	160039	160039	160039
160024	160038	1199	0	0	0	0	0	0	0	0	67	79937	25	80010	10	80000	10	80000	50	5677984	1	1	0	160019	0	160038	160038	139910	3	140018	80010	20	80000	20	240000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	2	0	0	10022	3	1	1	15	16	2	1	1	40	18	159983	0	15	13	24	160000	10	160039	160039	160039	160039	160039
160024	160038	1198	0	0	0	0	0	0	0	0	765	79937	25	80010	10	80000	10	80000	50	5677984	1	1	0	160019	0	160038	160038	139910	3	140018	80010	20	80000	20	240000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	3	1	1	16	16	2	1	1	34	16	159983	0	15	13	8	160000	10	160039	160039	160039	160039	160039
160024	160038	1199	0	0	0	0	0	0	0	9	67	79937	25	80010	10	80000	10	80000	50	5677984	1	1	0	160019	0	160038	160038	139910	3	140018	80010	20	80000	20	240000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	3	1	1	15	16	2	1	1	34	14	159983	0	15	13	8	160000	10	160039	160039	160039	160039	160039
160024	160038	1198	0	0	0	0	0	0	0	0	67	79937	25	80010	10	80012	10	80000	50	5677984	1	1	0	160019	0	160064	160038	139910	3	140018	80010	20	80000	20	240000	160098	160038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10050	3	2	2	13	16	4	2	2	13	15	159983	0	30	13	8	160000	10	160039	160039	160039	160039	160039
160024	160038	1198	0	0	0	0	0	0	0	0	67	79937	25	80010	10	80012	10	80000	50	5677984	1	1	0	160019	0	160038	160038	139910	3	140018	80010	20	80000	20	240000	160038	160098	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	3	1	1	13	17	2	1	1	37	11	159983	0	15	26	16	160000	10	160039	160039	160039	160039	160039
160024	160038	1199	0	0	0	0	0	0	0	0	73	79937	25	80010	10	80000	10	80000	50	5677984	0	1	0	160019	0	160038	160038	139910	3	140018	80010	20	80000	20	240000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	6	2	2	14	16	4	2	2	43	15	159983	0	30	26	16	160000	10	160039	160039	160039	160039	160039
160024	160038	1199	0	0	0	0	0	0	0	0	67	79937	25	80010	10	80000	10	80000	50	5677984	1	1	0	160019	0	160038	160038	139910	3	140018	80010	20	80000	20	240000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	3	1	1	15	16	2	1	1	36	14	159983	0	15	13	8	160000	10	160039	160039	160039	160039	160039
160024	160038	1198	0	0	0	0	0	0	0	0	100	79937	25	80010	10	80012	10	80044	50	5677984	1	1	0	160019	0	160038	160038	139910	37	140018	80010	20	80000	20	240000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	3	1	1	15	17	23	2	1	13	13	159983	0	15	13	8	160000	10	160039	160039	160039	160039	160039

Test 6: throughput

Count: 16

Code:

  sha512h2 q0, q16, v17.2d
  sha512h2 q1, q16, v17.2d
  sha512h2 q2, q16, v17.2d
  sha512h2 q3, q16, v17.2d
  sha512h2 q4, q16, v17.2d
  sha512h2 q5, q16, v17.2d
  sha512h2 q6, q16, v17.2d
  sha512h2 q7, q16, v17.2d
  sha512h2 q8, q16, v17.2d
  sha512h2 q9, q16, v17.2d
  sha512h2 q10, q16, v17.2d
  sha512h2 q11, q16, v17.2d
  sha512h2 q12, q16, v17.2d
  sha512h2 q13, q16, v17.2d
  sha512h2 q14, q16, v17.2d
  sha512h2 q15, q16, v17.2d

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0002

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	320038	2397	0	0	0	0	0	61	159937	25	160100	100	160000	100	160000	500	11357984	0	320019	0	320038	320038	299888	0	3	299996	160100	200	160000	200	480216	320038	320038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	0	10110	2	49	1	1	319969	0	2	160000	100	320039	320039	320039	320039	320039
160204	320038	2397	0	0	0	708	0	953	159937	25	160100	100	160000	100	160000	500	11357984	0	320019	0	320184	320038	299888	0	21	299996	160100	200	160000	200	480000	320087	320038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	0	10110	1	16	1	1	320116	3	0	160000	100	320039	320039	320039	320039	320039
160204	320038	2397	0	0	0	0	0	61	159937	25	160100	100	160000	100	160000	500	11357984	0	320019	3	320038	320038	299888	0	3	299996	160100	200	160000	200	480000	320038	320038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	0	10110	1	16	1	1	319969	0	0	160000	100	320039	320039	320039	320039	320085
160204	320038	2397	0	0	0	0	0	61	159937	25	160100	100	160000	100	160000	500	11357984	0	320019	0	320038	320086	299888	0	3	299996	160100	200	160072	200	480000	320038	320038	2	1	160201	100	99	100	100	160000	100	0	0	0	0	119	0	0	0	0	0	10110	2	16	1	1	319969	0	0	160000	100	320039	320039	320039	320039	320039
160204	320038	2431	0	0	0	0	0	61	159937	25	160100	119	160000	100	160000	500	11357848	0	320019	0	320038	320038	299888	0	3	299996	160100	200	160000	200	480000	320038	320038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	0	10110	2	16	1	1	319969	0	0	160000	100	320039	320039	320039	320039	320039
160204	320038	2397	0	0	0	0	0	726	159937	25	160100	100	160000	100	160000	500	11357984	1	320019	0	320038	320038	299888	0	3	299996	160147	200	160000	200	480000	320038	320038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	0	10110	1	16	1	1	319969	0	0	160000	100	320039	320039	320039	320039	320039
160204	320038	2397	0	0	0	0	0	61	159937	25	160100	100	160000	100	160000	500	11357984	0	320019	0	320038	320038	299888	0	3	299996	160100	200	160000	200	480000	320038	320038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	0	10110	2	49	1	1	319969	0	0	160000	100	320039	320039	320039	320039	320039
160205	320038	2397	0	0	1	15	0	726	159937	25	160100	100	160000	100	160000	500	11357984	1	320019	0	320038	320038	299888	0	3	299996	160100	200	160000	200	480000	320038	320038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	6	0	0	0	0	0	10110	1	16	1	1	319969	0	0	160000	100	320039	320039	320039	320039	320039
160204	320038	2397	0	0	0	279	0	61	159937	25	160100	100	160000	100	160000	500	11357984	0	320019	0	320038	320038	299888	0	3	299996	160100	200	160000	200	480000	320038	320038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	0	10110	2	16	1	1	319969	0	0	160000	100	320039	320039	320039	320039	320039
160204	320038	2397	0	0	0	18	0	61	159937	25	160100	100	160000	100	160000	500	11357984	1	320019	0	320038	320038	299888	0	3	299996	160100	200	160000	200	480000	320038	320038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	0	0	10110	2	16	0	1	319969	0	0	160000	100	320039	320039	320039	320039	320039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0002

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	320038	2397	0	0	73	159937	25	160010	10	160000	10	160000	50	11357984	0	1	5	320019	0	320038	320038	299910	0	3	300018	160010	20	160000	20	480000	320038	320038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	13	5	1	6	16	1	1	1	5	4	319969	0	21	19	10	160000	10	320039	320039	320039	320039	320039
160024	320038	2398	0	0	67	159937	25	160010	10	160000	10	160000	50	11357984	1	1	10	320019	0	320038	320038	299910	0	3	300018	160010	20	160000	20	480000	320038	320038	1	1	160021	10	9	10	10	160000	10	0	0	1	0	0	0	0	0	10022	13	4	1	5	16	1	1	1	3	7	319969	0	21	19	10	160000	10	320039	320039	320039	320039	320039
160024	320038	2398	0	0	88	159937	25	160010	10	160000	10	160000	50	11357984	1	1	10	320019	0	320038	320038	299910	0	3	300018	160010	20	160000	20	480000	320038	320038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	13	5	1	3	16	1	1	1	5	7	319969	0	21	19	22	160000	10	320039	320039	320039	320039	320039
160024	320084	2397	0	0	67	159937	25	160010	10	160000	10	160000	50	11357984	1	1	10	320019	0	320038	320038	299910	0	3	300018	160010	20	160000	20	480000	320038	320038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	1	0	0	10024	16	6	2	9	120	2	2	1	3	7	319969	0	42	38	10	160000	10	320039	320039	320523	320136	320426
160024	320038	2398	1	0	67	159937	25	160010	10	160000	10	160046	50	11357984	1	1	10	320019	0	320038	320038	299910	0	3	300018	160010	20	160000	20	480000	320038	320038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	13	5	2	6	16	1	1	1	4	7	319969	0	21	19	10	160000	10	320039	320039	320039	320039	320039
160024	320038	2397	0	9	67	159937	25	160010	12	160000	12	160000	60	11357984	1	1	10	320019	0	320038	320038	299910	0	3	300018	160010	20	160000	20	480000	320038	320038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10052	13	6	1	7	16	1	1	1	6	4	319969	0	21	19	10	160000	10	320039	320039	320039	320039	320039
160024	320038	2397	0	0	738	159937	25	160010	10	160000	10	160000	50	11357984	1	1	10	320019	0	320038	320038	299910	0	3	300018	160010	20	160000	20	480000	320038	320038	3	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10024	16	7	2	5	16	2	2	2	5	4	319969	0	42	38	20	160000	10	320039	320039	320039	320039	320039
160024	320038	2397	0	0	67	159937	25	160010	10	160000	10	160000	50	11357984	1	1	10	320019	0	320038	320038	299910	0	3	300018	160010	20	160000	20	480000	320038	320038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	13	6	1	5	16	1	1	1	6	5	319969	0	21	19	10	160000	10	320039	320039	320039	320039	320039
160024	320038	2397	0	0	732	159937	25	160010	10	160000	10	160000	50	11357984	1	1	10	320019	0	320038	320038	299910	0	3	300018	160010	20	160000	20	480000	320038	320038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	13	6	1	3	16	1	1	1	5	8	319969	0	21	19	10	160000	10	320039	320039	320039	320039	320039
160024	320038	2397	0	0	67	159937	25	160010	10	160000	10	160000	50	11357984	1	1	10	320019	0	320038	320086	299910	0	3	300018	160010	20	160000	20	480000	320086	320038	1	1	160021	10	9	10	10	160000	10	0	0	2	0	0	1	0	1	10042	13	2	6	6	17	1	1	1	6	5	320043	0	21	22	10	160000	10	320039	320039	320039	320039	320039

SHA512H2

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations