Firestorm: SHA512SU0 measurements

Code:

  sha512su0 v0.2d, v1.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	16	0	0	61	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	1969	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	1969	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	937	25	1000	1000	1000	68984	1	2018	2037	2037	1788	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	75	2	16	1	1	1969	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	937	25	1000	1000	1000	68984	1	2018	2037	2037	1788	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	1969	1000	2038	2038	2038	2038	2038
1004	2037	15	1	0	61	937	25	1000	1000	1000	68984	1	2018	2037	2037	1787	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	1969	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	937	25	1000	1000	1000	68984	1	2018	2037	2037	1787	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	1969	1000	2038	2038	2038	2038	2038
1004	2037	16	0	0	61	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	1969	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	937	25	1000	1000	1000	68984	1	2018	2037	2037	1787	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	1969	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	61	937	25	1000	1000	1000	68984	1	2018	2037	2037	1788	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	1969	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	82	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	0	0	73	1	16	1	1	1969	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->1

Code:

  sha512su0 v0.2d, v1.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	61	9937	25	10100	100	10000	100	10000	500	707984	20018	20037	20037	18638	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	2	16	2	2	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	61	9937	25	10100	100	10000	100	10000	500	707984	20054	20037	20037	18638	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	1	0	710	2	16	2	2	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	61	9937	25	10100	100	10000	100	10000	500	707984	20018	20037	20037	18638	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	2	16	2	2	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	61	9937	25	10100	100	10000	100	10000	500	707984	20018	20037	20037	18638	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	2	16	2	2	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	61	9937	25	10100	100	10000	100	10000	500	707984	20018	20037	20037	18638	3	18745	10148	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	1	0	710	2	16	2	2	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	61	9937	25	10100	100	10000	100	10000	500	707984	20018	20037	20037	18638	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	2	16	2	2	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	61	9937	25	10100	100	10000	100	10000	500	707984	20018	20037	20037	18638	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	1	0	710	2	16	2	2	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	61	9937	25	10100	100	10000	100	10000	500	707984	20018	20037	20037	18638	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	2	16	2	2	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	61	9937	25	10100	100	10000	100	10000	500	707984	20018	20037	20037	18638	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	2	16	2	2	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	61	9937	25	10100	100	10000	100	10000	500	707984	20018	20037	20037	18638	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	2	16	2	2	19967	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	0	0	0	0	84	9937	25	10010	10	10000	10	10000	50	707984	0	20018	20037	20037	18660	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	4	0	0	0	640	2	16	2	2	19969	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	0	20018	20037	20037	18660	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	19969	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	9937	25	10010	10	10000	11	10000	50	707984	1	20018	20037	20037	18660	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	3	0	640	2	16	2	2	20005	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20018	20037	20037	18660	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	3	19969	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	0	20018	20037	20037	18660	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	1	0	0	0	640	2	16	2	2	19969	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	0	20018	20037	20037	18660	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	3	0	640	2	16	2	2	19969	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20018	20037	20037	18660	3	18767	10056	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	3	0	654	2	16	2	2	19969	0	10000	10	20038	20038	20038	20084	20038
10024	20037	150	0	0	1	0	0	0	61	9937	25	10037	10	10012	10	10000	50	707984	0	20018	20037	20037	18660	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	2	0	0	0	0	640	2	16	2	2	19969	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	103	9937	25	10010	10	10000	10	10000	50	707984	0	20018	20037	20037	18660	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	19969	0	10000	10	20231	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	0	20018	20037	20037	18660	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	19969	0	10000	10	20038	20038	20038	20038	20038

Test 3: Latency 1->2

Code:

  sha512su0 v0.2d, v0.2d

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	4	0	0	61	9936	25	10126	100	10000	100	10000	500	707921	1	20018	20037	20037	18644	7	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	0	0	19978	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	9936	25	10100	100	10000	100	10000	500	707921	0	20018	20037	20037	18644	7	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	0	16	0	0	19978	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	9936	25	10100	100	10000	100	10000	500	707921	1	20018	20037	20037	18644	7	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	0	0	19979	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	9936	25	10100	100	10000	100	10000	500	707921	0	20018	20037	20037	18644	7	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	0	0	19979	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	9936	25	10100	100	10000	100	10000	500	707921	1	20018	20037	20037	18644	7	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	0	16	0	0	19979	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	9936	25	10100	100	10000	100	10000	500	707921	0	20018	20037	20037	18644	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	0	16	0	0	19979	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	9936	25	10100	100	10000	100	10000	500	707921	1	20018	20037	20037	18644	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	0	16	0	0	19978	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	9936	25	10100	100	10000	100	10000	500	707921	1	20018	20037	20037	18644	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	0	0	19979	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	652	9936	25	10100	100	10000	100	10000	500	707921	0	20018	20037	20037	18644	7	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	0	0	19978	10000	100	20038	20038	20038	20038	20038
10204	20037	149	0	0	0	61	9936	25	10100	100	10000	100	10000	500	707921	0	20018	20037	20037	18644	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	0	0	19979	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	170	9936	25	10010	10	10000	10	10000	50	707921	0	20018	20037	20037	18659	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19968	10000	10	20038	20038	20038	20038	20038
10024	20037	150	9	785	9936	25	10010	10	10000	10	10000	50	707921	1	20018	20037	20037	18659	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19968	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	9936	25	10010	10	10000	10	10000	50	707921	0	20018	20037	20037	18659	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19968	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	9936	25	10010	10	10000	10	10000	50	707921	0	20018	20037	20037	18659	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19968	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	9936	25	10010	10	10000	10	10000	50	707921	0	20018	20037	20037	18659	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	2714	640	2	16	2	2	19968	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	87	9936	25	10010	10	10000	10	10000	50	707921	0	20018	20037	20037	18659	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19968	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	9936	25	10010	10	10000	10	10000	50	707921	0	20018	20037	20037	18659	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19968	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	9936	25	10010	10	10000	10	10000	50	707921	0	20018	20037	20037	18659	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19968	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	170	9936	25	10010	10	10000	10	10000	50	707921	0	20018	20037	20037	18659	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19968	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	758	9936	25	10010	10	10000	10	10000	50	707921	0	20018	20037	20037	18659	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19968	10000	10	20038	20038	20038	20038	20038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sha512su0 v0.2d, v8.2d
  movi v1.16b, 0
  sha512su0 v1.2d, v8.2d
  movi v2.16b, 0
  sha512su0 v2.2d, v8.2d
  movi v3.16b, 0
  sha512su0 v3.2d, v8.2d
  movi v4.16b, 0
  sha512su0 v4.2d, v8.2d
  movi v5.16b, 0
  sha512su0 v5.2d, v8.2d
  movi v6.16b, 0
  sha512su0 v6.2d, v8.2d
  movi v7.16b, 0
  sha512su0 v7.2d, v8.2d

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	80039	599	0	0	0	0	0	0	0	465	25	80100	100	80000	100	80000	500	640000	0	80167	80038	80038	59970	6	59991	80100	200	80008	200	160016	80038	80038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10117	0	16	0	0	80035	0	160000	100	80039	80039	80039	80039	80039
160204	80038	599	0	0	0	0	0	0	0	38	25	80100	100	80000	100	80000	500	640000	1	80019	80038	80038	59970	6	59991	80100	200	80008	200	160016	80038	80038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10117	0	16	0	0	80035	0	160000	100	80039	80039	80039	80039	80039
160204	80038	599	0	0	0	0	12	0	0	975	25	80100	100	80000	100	80000	500	640000	0	80019	80038	80038	59970	6	59991	80100	200	80008	200	160016	80038	80038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10117	0	16	0	0	80035	0	160000	100	80039	80039	80039	80039	80039
160204	80038	600	0	0	0	0	0	0	0	80	25	80100	100	80000	100	80000	500	640195	1	80019	80182	80038	59970	6	59991	80125	200	80116	200	160088	80134	80038	6	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10117	0	16	0	0	80035	0	160000	100	80039	80039	80039	80039	80039
160204	80038	599	0	0	0	0	0	0	0	38	25	80100	100	80000	100	80000	500	640000	0	80019	80038	80038	59970	6	59991	80100	200	80008	200	160016	80038	80038	1	1	160201	100	99	100	100	160000	100	0	5	0	3	1	1	1	10117	0	16	0	0	80035	0	160000	100	80039	80039	80039	80039	80039
160204	80038	600	0	0	0	0	0	0	0	38	25	80100	100	80023	100	80000	500	640000	1	80019	80038	80038	59970	6	59991	80100	200	80008	200	160016	80038	80038	1	1	160201	100	99	100	100	160000	100	0	21	0	0	1	1	1	10117	0	16	0	0	80035	0	160000	100	80039	80039	80039	80039	80039
160204	80038	600	0	0	0	0	0	0	0	38	25	80100	100	80000	100	80000	500	640000	0	80019	80038	80038	59970	6	59991	80100	200	80008	200	160016	80038	80038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10117	0	16	0	0	80035	0	160000	100	80039	80039	80039	80039	80039
160204	80038	599	0	0	0	0	0	0	0	38	25	80100	100	80000	100	80000	500	640000	0	80019	80038	80038	59970	6	59991	80100	200	80008	200	160016	80038	80038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10117	0	16	0	0	80035	0	160000	100	80039	80039	80039	80039	80039
160204	80038	600	0	0	0	0	126	0	0	745	25	80100	100	80000	100	80050	500	640000	0	80019	80038	80087	59961	9	59978	80200	200	80011	200	160088	80135	80038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	2	2	2	10127	1	23	1	1	80035	0	160000	100	80039	80039	80039	80039	80039
160204	80038	599	0	0	0	0	0	0	0	71	43	80123	100	80000	100	80000	500	640000	1	80019	80038	80038	59961	9	59979	80100	202	80011	200	160022	80038	80038	4	1	160201	100	99	100	100	160000	100	0	0	0	0	2	2	2	10128	0	23	1	1	80035	0	160000	100	80039	80039	80039	80039	80039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	80039	599	0	0	0	55	25	80010	10	80000	10	80000	50	640000	1	1	80019	0	80038	80038	59986	3	60018	80010	20	80000	20	160000	80038	80038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	3	54	3	4	16	2	1	1	2	3	80035	15	10	160000	10	80039	80039	80039	80039	80039
160024	80038	599	0	0	0	55	25	80010	10	80000	10	80000	50	640000	1	1	80019	0	80038	80038	59986	3	60018	80010	20	80000	20	160000	80038	80038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	3	45	3	3	17	2	1	1	3	2	80035	15	20	160000	10	80039	80039	80039	80039	80039
160024	80038	599	0	0	0	55	25	80010	10	80000	10	80000	50	640000	1	1	80019	0	80038	80038	59986	3	60018	80010	20	80000	20	160000	80038	80038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	3	52	3	3	16	2	1	1	3	3	80035	15	10	160000	10	80039	80039	80039	80039	80097
160024	80038	599	0	0	0	55	25	80010	10	80000	10	80000	50	640000	1	1	80019	0	80038	80038	59986	3	60018	80010	20	80000	20	160000	80038	80038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	3	46	3	2	16	2	1	1	3	3	80035	15	10	160000	10	80039	80039	80039	80039	80039
160024	80038	600	0	0	0	55	25	80010	10	80000	10	80000	50	640000	1	1	80019	0	80038	80038	59986	3	60018	80010	20	80000	20	160000	80038	80038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	3	48	3	2	16	2	1	1	3	2	80035	15	20	160000	10	80039	80039	80039	80039	80039
160024	80038	599	0	0	0	196	25	80010	10	80000	10	80000	50	640000	1	1	80019	0	80038	80038	59986	3	60018	80010	20	80000	20	160000	80038	80038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	3	48	3	3	16	2	1	1	3	3	80035	15	10	160000	10	80039	80039	80039	80039	80039
160024	80038	600	0	0	0	55	25	80010	10	80000	10	80000	50	640000	1	1	80019	0	80038	80038	59986	3	60018	80010	20	80000	20	160000	80038	80038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	3	47	3	3	16	2	1	1	2	3	80035	15	10	160000	10	80039	80039	80039	80039	80039
160024	80038	599	0	0	0	55	25	80010	10	80023	10	80000	50	640000	1	1	80019	0	80038	80038	59986	3	60018	80010	20	80000	20	160000	80038	80038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	3	49	3	4	16	2	1	1	2	3	80035	15	10	160000	10	80039	80039	80039	80039	80039
160024	80038	599	0	0	0	55	25	80010	10	80000	10	80000	50	640000	1	1	80019	0	80038	80038	59986	3	60018	80010	20	80000	20	160000	80038	80038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	3	48	3	2	16	2	1	1	4	3	80035	15	10	160000	10	80039	80039	80039	80039	80039
160024	80038	600	0	0	0	55	25	80010	10	80000	10	80000	50	640000	1	1	80019	0	80038	80038	59986	3	60018	80010	20	80000	20	160000	80038	80038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	3	48	3	3	16	2	2	1	3	3	80035	15	10	160000	10	80039	80039	80039	80039	80039

Test 5: throughput

Count: 16

Code:

  sha512su0 v0.2d, v16.2d
  sha512su0 v1.2d, v16.2d
  sha512su0 v2.2d, v16.2d
  sha512su0 v3.2d, v16.2d
  sha512su0 v4.2d, v16.2d
  sha512su0 v5.2d, v16.2d
  sha512su0 v6.2d, v16.2d
  sha512su0 v7.2d, v16.2d
  sha512su0 v8.2d, v16.2d
  sha512su0 v9.2d, v16.2d
  sha512su0 v10.2d, v16.2d
  sha512su0 v11.2d, v16.2d
  sha512su0 v12.2d, v16.2d
  sha512su0 v13.2d, v16.2d
  sha512su0 v14.2d, v16.2d
  sha512su0 v15.2d, v16.2d

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0002

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	160039	1199	0	0	0	88	38	25	160100	100	160000	100	160000	500	1280000	0	160019	160038	160086	139971	0	6	139992	160100	200	160008	200	320016	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10117	2	16	2	1	160035	160000	100	160039	160039	160039	160039	160039
160204	160038	1199	0	0	0	0	38	25	160100	100	160000	100	160000	500	1280000	1	160019	160038	160038	139971	0	6	139992	160100	200	160008	200	320016	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	3	1	1	1	10117	2	16	2	2	160035	160000	100	160039	160039	160039	160039	160039
160204	160038	1199	0	0	0	0	418	38	160100	100	160000	100	160000	500	1280000	1	160019	160038	160038	139994	0	6	139992	160100	200	160008	200	320016	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10117	2	16	2	1	160035	160000	100	160039	160039	160039	160039	160039
160204	160038	1199	0	1	0	0	38	25	160100	100	160000	100	160000	500	1280000	1	160019	160038	160038	139971	0	6	139992	160100	200	160008	200	320016	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10131	2	16	2	2	160035	160000	100	160039	160039	160039	160039	160039
160204	160038	1198	0	0	0	0	608	25	160100	100	160000	100	160000	500	1280000	1	160019	160038	160038	139971	0	6	139992	160100	200	160008	200	320016	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10117	2	16	2	1	160035	160000	100	160039	160039	160039	160039	160039
160204	160038	1199	0	0	0	0	38	25	160100	100	160000	100	160000	500	1280000	0	160019	160038	160038	139971	0	6	139992	160100	200	160008	200	320016	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10117	2	16	1	2	160035	160000	100	160039	160039	160039	160039	160039
160204	160038	1199	0	0	0	0	755	25	160100	100	160000	100	160000	500	1280000	1	160019	160038	160038	139971	0	6	139992	160100	200	160008	200	320016	160085	160038	1	1	160201	100	99	100	100	160000	100	0	1	0	0	1	1	1	10117	1	16	1	2	160035	160000	100	160039	160039	160039	160039	160039
160204	160038	1199	0	0	0	0	1986	25	160100	100	160000	100	160000	500	1280000	0	160019	160038	160038	139971	0	6	139992	160100	200	160008	200	320016	160038	160038	1	1	160202	100	99	100	100	160000	100	0	0	0	0	1	1	1	10117	2	16	1	2	160035	160000	100	160039	160039	160039	160039	160039
160204	160038	1199	0	0	27	0	38	25	160100	100	160000	100	160000	500	1280000	0	160019	160038	160038	139971	0	16	139992	160100	200	160008	200	320016	160038	160038	1	1	160201	100	99	100	100	160000	100	2	2	2	1098	1	1	1	10131	2	16	1	2	160035	160000	100	160039	160039	160039	160039	160039
160204	160038	1199	0	0	12	0	38	25	160100	100	160092	100	160000	500	1280585	1	160019	160038	160038	139971	0	6	139992	160100	200	160008	200	320016	160038	160038	1	1	160201	100	99	100	100	160000	100	0	2	0	0	1	1	1	10117	2	16	2	1	160035	160000	100	160039	160039	160086	160039	160039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0002

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	160038	1199	0	0	0	0	55	25	160010	10	160016	10	160000	50	1280000	1	1	0	160019	160038	160038	139986	3	140018	160010	20	160000	20	320000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	327	0	10022	3	1	1	13	16	1	1	1	10	21	160082	20	16	160000	10	160039	160087	160039	160039	160039
160024	160038	1198	0	0	0	0	720	25	160010	10	160000	10	160000	50	1280000	1	1	0	160019	160038	160038	139986	3	140018	160010	20	160000	20	320000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	315	0	10022	21	1	1	21	16	2	1	2	9	21	160033	20	16	160000	10	160039	160039	160039	160039	160039
160024	160038	1198	0	0	0	0	61	25	160010	10	160000	10	160000	50	1280000	0	1	0	160019	160038	160038	139986	3	140018	160010	20	160000	20	320000	160038	160038	1	1	160021	10	9	10	10	160000	10	2	348	0	10024	3	1	1	9	16	4	2	2	10	19	160033	40	32	160000	10	160039	160039	160039	160039	160039
160024	160038	1199	0	0	0	0	61	25	160010	10	160000	10	160000	50	1280000	1	1	0	160019	160038	160038	139986	3	140018	160010	20	160000	20	320000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	381	0	10024	3	1	1	21	16	2	1	1	9	21	160033	20	32	160000	10	160039	160039	160039	160039	160039
160024	160038	1200	0	0	0	0	61	25	160010	10	160000	10	160000	50	1280000	0	1	0	160019	160038	160038	139986	3	140018	160010	20	160000	20	320000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	399	0	10022	6	2	1	21	16	4	4	2	7	21	160033	20	16	160000	10	160039	160039	160039	160039	160039
160024	160038	1199	0	0	0	0	55	25	160010	10	160000	10	160000	50	1280000	0	1	0	160019	160038	160038	139986	3	140018	160010	20	160000	20	320000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	345	0	10022	3	1	1	8	16	2	1	1	22	17	160033	40	16	160000	10	160039	160039	160039	160039	160039
160024	160038	1199	0	0	0	0	55	25	160010	10	160000	10	160000	50	1280000	1	1	0	160019	160038	160038	139986	3	140018	160010	20	160000	20	320000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	21	1	10022	3	1	1	22	16	2	1	1	22	8	160033	20	17	160000	10	160039	160039	160039	160039	160039
160024	160038	1199	0	0	0	0	720	25	160010	10	160000	10	160000	50	1280000	1	1	0	160067	160038	160038	139986	3	140018	160010	20	160000	20	320000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	276	0	10022	3	1	2	22	16	2	1	1	7	19	160033	20	16	160000	10	160039	160039	160039	160039	160039
160024	160038	1199	0	0	150	0	55	25	160010	10	160000	10	160000	50	1280000	1	1	0	160019	160038	160038	139986	3	140018	160010	20	160000	20	320000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	21	0	10024	3	2	2	21	16	2	1	2	9	19	160033	40	16	160000	10	160039	160039	160039	160039	160085
160024	160038	1200	0	0	0	0	530	25	160010	10	160000	10	160000	50	1280000	0	1	0	160019	160038	160038	139986	3	140018	160010	20	160000	20	320086	160038	160086	1	1	160021	10	9	10	10	160000	10	0	141	0	10024	3	1	1	21	16	2	1	2	25	10	160033	20	16	160000	10	160039	160039	160039	160039	160039

SHA512SU0

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations