Firestorm: SHA512SU1 measurements

Code:

  sha512su1 v0.2d, v1.2d, v2.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	15	0	82	937	25	1000	1000	1000	68984	1	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	3	0	73	1	16	1	1	1969	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	937	25	1000	1000	1000	68984	1	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	4	0	73	1	16	1	1	1969	1000	2038	2038	2038	2038	2038
1004	2037	15	0	103	937	25	1000	1000	1000	68984	1	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1969	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	937	25	1000	1000	1000	68984	1	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1969	1000	2038	2038	2038	2038	2038
1004	2037	15	3	61	937	25	1000	1000	1000	68984	1	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1969	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	937	25	1000	1000	1000	68984	1	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	1	0	73	1	16	1	1	1969	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	2	0	73	1	16	1	1	1969	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	937	25	1000	1000	1000	68984	1	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1969	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	6	73	1	16	1	1	1969	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	937	25	1000	1000	1000	68984	0	2018	2037	2037	1788	3	1895	1000	1000	3000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1969	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->1

Code:

  sha512su1 v0.2d, v1.2d, v2.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	0	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	27	117	0	710	1	2	16	2	2	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	0	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	2	710	1	2	16	2	2	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	1	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	3	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	0	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	3	0	61	9937	25	10100	100	10000	100	10000	500	707984	1	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	34	9	0	712	1	2	16	2	2	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	1	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	9937	25	10100	100	10000	113	10000	500	707984	1	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	3	0	0	710	1	2	16	2	2	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	1	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	27	0	710	1	2	16	2	2	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	631	9937	25	10100	100	10000	100	10000	500	707984	0	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	12	0	710	1	2	16	2	2	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	0	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	19967	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	149	0	0	0	0	726	9937	25	10010	10	10000	10	10000	50	707984	1	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	7	3	0	640	2	16	2	2	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	3	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	2	0	1	0	0	640	2	16	2	2	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	6	0	0	640	2	16	2	2	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	4	0	0	640	2	16	2	2	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	9	0	0	640	3	16	2	2	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	21	3	0	640	2	16	2	3	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	1	0	0	0	82	9937	25	10010	10	10000	10	10000	50	707984	1	20054	20037	20037	18660	3	18767	10010	20	10056	20	30177	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	2	0	6	0	640	2	16	3	2	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	3	0	640	2	16	2	2	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	3	0	640	2	16	2	2	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	3	19969	10000	10	20038	20038	20038	20038	20038

Test 3: Latency 1->2

Code:

  sha512su1 v0.2d, v0.2d, v1.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	0	61	9937	25	10100	100	10000	102	10044	500	707984	0	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	2	1	10201	100	99	100	100	10000	100	0	1	0	710	1	16	1	1	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	1	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	1	0	710	1	16	1	1	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	0	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	2	1	0	710	1	16	1	1	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	726	9937	25	10100	100	10000	100	10132	500	707984	0	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	4	6	710	1	16	1	1	19967	10000	100	20038	20038	20038	20181	20038
10204	20037	150	0	0	0	61	9937	25	10100	100	10000	100	10000	626	707984	0	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	1	0	710	1	16	1	1	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	0	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	1	3	710	1	16	1	1	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	0	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20133	20085	1	1	10201	100	99	100	100	10000	100	0	1	3	710	1	16	1	1	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	149	0	0	0	595	9937	25	10100	100	10000	100	10000	500	707984	0	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	1	3	710	1	16	1	2	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	1	0	61	9937	25	10100	100	10000	100	10000	500	707984	0	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	1	3	710	1	16	1	1	19967	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	12	61	9937	25	10100	100	10000	100	10000	500	707984	1	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20178	1	1	10201	100	99	100	100	10000	100	0	0	3	710	1	16	1	1	19967	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	61	9937	25	10010	10	10000	10	10000	50	707984	0	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	3	0	9	640	2	16	2	2	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19969	10000	10	20038	20038	20038	20038	20132
10024	20037	150	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	1	0	0	640	2	16	2	2	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	35	0	81	640	2	16	2	2	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	9937	25	10010	10	10000	10	10000	50	707984	0	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	9937	25	10010	10	10000	10	10000	50	707984	0	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	9937	25	10010	10	10000	10	10000	50	707984	0	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	24	0	3	640	3	16	2	2	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	9937	25	10010	10	10000	10	10000	50	707984	0	20018	20037	20037	18660	3	18767	10010	20	10000	20	30177	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19969	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	3721	9937	25	10010	10	10000	10	10000	50	707984	1	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19969	10000	10	20038	20038	20038	20038	20038

Test 4: Latency 1->3

Code:

  sha512su1 v0.2d, v1.2d, v0.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	18	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	1	0	0	0	1996	9937	25	10100	100	10000	100	10000	500	707984	0	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	2	16	1	1	19967	0	10000	100	20038	20038	20038	20038	20038
10204	20037	149	0	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	0	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	3	710	1	16	1	1	19967	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	0	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	0	710	1	16	1	1	19967	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	1	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	7	2940	710	1	16	1	1	19967	0	10000	100	20038	20038	20038	20038	20038
10204	20037	149	0	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	1	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19967	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	0	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19967	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	0	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19967	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	124	9937	25	10100	100	10000	120	10000	500	707984	0	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	27	3	710	1	16	1	1	19967	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	0	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	0	710	1	16	1	1	19967	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	9937	25	10100	100	10000	100	10000	500	707984	0	20018	20037	20037	18638	3	18745	10100	200	10000	200	30000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	19967	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	0	0	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19969	0	10000	10	20038	20038	20038	20038	20038
10024	20037	155	0	0	0	0	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19969	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	3	0	0	0	0	640	2	16	2	2	19969	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	1	0	0	0	0	640	2	16	2	2	19969	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	3	5	0	0	0	0	640	2	16	2	2	19969	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19969	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	38	0	90	0	0	640	2	16	2	2	19969	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19969	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19969	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	0	61	9937	25	10010	10	10000	10	10000	50	707984	1	20018	20037	20037	18660	3	18767	10010	20	10000	20	30000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	19969	0	10000	10	20038	20038	20038	20038	20038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  sha512su1 v0.2d, v8.2d, v9.2d
  movi v1.16b, 0
  sha512su1 v1.2d, v8.2d, v9.2d
  movi v2.16b, 0
  sha512su1 v2.2d, v8.2d, v9.2d
  movi v3.16b, 0
  sha512su1 v3.2d, v8.2d, v9.2d
  movi v4.16b, 0
  sha512su1 v4.2d, v8.2d, v9.2d
  movi v5.16b, 0
  sha512su1 v5.2d, v8.2d, v9.2d
  movi v6.16b, 0
  sha512su1 v6.2d, v8.2d, v9.2d
  movi v7.16b, 0
  sha512su1 v7.2d, v8.2d, v9.2d

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	66	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	80038	600	0	0	0	0	239	25	80100	100	80000	100	80000	500	640000	1	0	80019	80038	80038	59964	3	59996	80100	200	80000	200	240000	80038	80038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10110	2	16	1	1	80035	0	160000	100	80039	80039	80039	80039	80039
160204	80038	599	0	0	0	0	714	25	80100	100	80000	100	80000	500	640000	1	0	80019	80038	80038	59964	3	59996	80100	200	80000	200	240000	80038	80038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10110	1	16	1	1	80035	0	160000	100	80039	80039	80039	80039	80039
160204	80038	600	0	0	0	0	714	25	80100	100	80000	100	80000	500	640000	1	0	80019	80038	80038	59964	3	59996	80100	200	80000	200	240000	80038	80038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10110	1	16	1	1	80035	0	160000	100	80039	80039	80039	80039	80039
160204	80038	599	0	0	0	0	714	25	80100	100	80000	100	80000	500	640000	1	0	80019	80038	80038	59964	3	59996	80100	200	80000	200	240000	80038	80038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10110	1	16	1	1	80035	0	160000	100	80039	80039	80039	80039	80039
160204	80038	600	0	0	0	0	49	25	80100	100	80000	100	80000	500	640000	1	0	80019	80038	80038	59964	3	59996	80100	200	80000	200	240000	80038	80038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10110	1	16	1	1	80035	0	160000	100	80039	80039	80039	80039	80039
160204	80038	599	0	0	0	0	49	25	80100	100	80000	100	80000	500	640000	1	0	80019	80038	80038	59964	3	59996	80100	200	80000	200	240000	80038	80038	1	1	160201	100	99	100	100	160000	100	0	2	0	0	10110	2	16	1	1	80035	0	160000	100	80039	80039	80039	80039	80039
160204	80038	600	0	0	0	0	49	25	80100	100	80000	100	80000	500	640000	1	0	80019	80038	80038	59964	3	59996	80100	200	80000	200	240000	80038	80038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10110	1	16	1	1	80035	0	160000	100	80039	80039	80039	80039	80039
160204	80038	599	0	0	0	0	49	25	80100	100	80000	100	80000	500	640000	1	0	80019	80038	80038	59964	3	59996	80100	200	80000	200	240000	80038	80038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10110	1	16	1	1	80035	0	160000	100	80039	80039	80039	80039	80039
160204	80038	599	0	0	0	0	49	25	80100	100	80000	100	80000	500	640000	1	0	80019	80038	80038	59964	3	59996	80100	200	80000	200	240000	80038	80038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10110	1	16	1	1	80035	0	160000	100	80039	80039	80039	80039	80039
160204	80038	600	0	0	0	0	49	25	80100	100	80000	100	80000	500	640000	1	0	80019	80038	80038	59964	3	59996	80100	200	80000	200	240000	80038	80096	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10110	1	16	1	1	80035	0	160000	100	80039	80039	80039	80039	80039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	80038	600	0	55	25	80010	10	80000	10	80000	50	640000	1	1	10	80019	0	80038	80038	59986	3	60018	80010	20	80000	20	240000	80038	80038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	13	3	1	10	16	4	1	13	8	8	80035	0	15	10	160000	10	80039	80097	80039	80039	80039
160024	80038	599	0	55	25	80010	10	80000	10	80000	50	640000	0	1	10	80019	0	80038	80038	59986	3	60018	80010	20	80000	20	240000	80038	80038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	13	7	1	10	16	2	1	16	11	12	80035	0	15	10	160000	10	80039	80039	80039	80039	80039
160024	80038	600	0	55	25	80010	10	80000	10	80000	50	640000	1	1	10	80019	0	80038	80038	59986	3	60018	80010	20	80000	20	240000	80038	80038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10024	16	8	2	6	16	4	2	17	10	6	80035	0	15	20	160000	10	80039	80039	80039	80039	80039
160024	80038	600	0	55	25	80010	10	80000	10	80000	50	640000	1	1	10	80019	0	80038	80038	59986	3	60018	80010	20	80000	20	240000	80038	80038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	13	7	1	5	16	2	2	15	6	12	80035	0	15	10	160000	10	80039	80039	80039	80039	80039
160024	80038	599	0	55	25	80010	10	80000	10	80000	50	640000	0	1	10	80019	0	80038	80038	59986	3	60018	80010	20	80000	20	240000	80038	80038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	13	7	1	4	16	2	1	14	6	6	80035	0	15	20	160000	10	80039	80039	80039	80039	80039
160024	80038	600	0	55	25	80010	10	80000	10	80000	50	640000	1	1	10	80019	0	80038	80038	59986	3	60018	80010	20	80000	20	240000	80038	80038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	13	7	1	4	16	2	1	14	6	4	80035	0	15	20	160000	10	80039	80039	80039	80039	80039
160024	80038	600	0	720	25	80010	10	80000	10	80000	50	640000	1	1	10	80019	0	80038	80038	59986	3	60018	80010	20	80000	20	240000	80038	80038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	16	7	1	10	16	2	1	15	5	10	80035	0	15	10	160000	10	80039	80039	80039	80039	80039
160024	80038	600	0	55	25	80010	10	80000	10	80000	50	640000	1	1	10	80019	0	80038	80038	59986	3	60018	80010	20	80000	20	240000	80038	80038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	13	7	1	4	16	2	1	15	6	11	80035	0	30	10	160000	10	80039	80039	80039	80039	80039
160024	80038	599	0	61	25	80010	10	80000	10	80000	50	640000	1	1	10	80019	0	80038	80038	59986	3	60018	80010	20	80000	20	240000	80038	80038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	16	8	1	8	16	2	1	19	6	8	80035	0	15	20	160000	10	80039	80039	80039	80039	80039
160024	80038	600	0	55	25	80010	10	80000	10	80000	50	640000	1	1	10	80019	0	80038	80038	59986	3	60018	80010	20	80000	20	240000	80038	80038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	13	7	1	4	16	2	2	14	10	6	80035	0	15	10	160000	10	80039	80039	80039	80039	80039

Test 6: throughput

Count: 16

Code:

  sha512su1 v0.2d, v16.2d, v17.2d
  sha512su1 v1.2d, v16.2d, v17.2d
  sha512su1 v2.2d, v16.2d, v17.2d
  sha512su1 v3.2d, v16.2d, v17.2d
  sha512su1 v4.2d, v16.2d, v17.2d
  sha512su1 v5.2d, v16.2d, v17.2d
  sha512su1 v6.2d, v16.2d, v17.2d
  sha512su1 v7.2d, v16.2d, v17.2d
  sha512su1 v8.2d, v16.2d, v17.2d
  sha512su1 v9.2d, v16.2d, v17.2d
  sha512su1 v10.2d, v16.2d, v17.2d
  sha512su1 v11.2d, v16.2d, v17.2d
  sha512su1 v12.2d, v16.2d, v17.2d
  sha512su1 v13.2d, v16.2d, v17.2d
  sha512su1 v14.2d, v16.2d, v17.2d
  sha512su1 v15.2d, v16.2d, v17.2d

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0002

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	160038	1199	0	0	0	0	38	25	160100	100	160000	100	160000	500	1280000	1	160019	160038	160038	139971	0	6	139992	160100	200	160008	200	480024	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10117	1	16	2	0	0	160035	0	160000	100	160039	160039	160039	160039	160039
160204	160038	1199	0	0	0	0	38	25	160100	100	160000	100	160000	500	1280000	1	160019	160038	160038	139971	0	6	139992	160100	200	160008	200	480024	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10117	0	16	0	0	0	160035	0	160000	100	160039	160039	160039	160039	160039
160204	160038	1198	0	0	0	0	70	25	160100	100	160000	100	160000	500	1280000	1	160019	160038	160038	139964	0	3	139996	160100	200	160000	200	480000	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10131	1	16	0	1	1	160035	0	160000	100	160039	160039	160039	160039	160039
160204	160038	1199	0	0	0	0	49	25	160100	100	160000	100	160000	500	1280000	1	160019	160038	160038	139964	0	3	139996	160100	200	160000	200	480000	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10110	1	16	0	1	1	160035	0	160000	100	160039	160039	160039	160039	160039
160204	160038	1199	0	0	0	0	49	25	160100	100	160000	100	160000	500	1280000	1	160019	160038	160038	139964	0	3	139996	160100	200	160000	200	480000	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10110	1	16	2	1	1	160035	0	160000	100	160039	160039	160039	160039	160039
160204	160038	1198	0	0	0	0	49	25	160100	100	160000	100	160000	500	1280000	1	160019	160038	160038	139964	0	3	139996	160100	200	160000	200	480000	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	2	10110	1	16	0	1	1	160035	0	160000	100	160039	160039	160039	160039	160039
160204	160038	1199	0	0	0	0	49	25	160100	100	160000	100	160000	500	1280000	1	160019	160038	160038	139964	0	3	139996	160100	200	160000	200	480000	160038	160038	1	1	160202	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10110	1	16	0	1	1	160035	0	160000	100	160039	160039	160039	160039	160039
160204	160038	1199	0	0	0	0	232	25	160100	100	160000	100	160000	500	1280000	1	160019	160038	160038	139964	0	3	139996	160100	200	160000	200	480000	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10110	1	16	0	1	1	160035	0	160000	100	160039	160039	160039	160039	160039
160204	160038	1199	0	0	0	0	334	25	160100	100	160000	100	160000	500	1280000	1	160019	160038	160038	139964	0	3	139996	160100	200	160000	200	480000	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	0	10110	1	16	0	1	1	160035	0	160000	100	160039	160039	160039	160039	160039
160204	160038	1198	0	0	0	0	135	25	160100	100	160000	100	160000	500	1280000	1	160019	160038	160038	139995	0	3	139996	160100	200	160000	200	480000	160038	160038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	0	0	10110	1	16	0	1	1	160035	0	160000	100	160039	160039	160039	160039	160039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0002

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	160038	1199	1	0	0	55	25	160010	10	160000	10	160000	50	1280000	1	1	5	160019	0	160038	160038	139986	0	3	140018	160010	20	160000	20	480000	160038	160038	1	1	160021	10	9	10	10	160000	10	2	0	0	0	0	10023	8	4	1	1	45	16	1	1	1	27	37	160033	21	17	160000	10	160039	160039	160039	160039	160039
160024	160038	1199	0	0	0	78	25	160010	10	160000	10	160000	50	1280000	1	1	5	160019	0	160038	160038	139986	0	3	140018	160010	20	160000	20	480000	160086	160038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10023	8	5	1	1	39	16	1	1	1	32	37	160033	21	17	160000	10	160039	160039	160039	160039	160039
160024	160038	1199	1	0	0	78	25	160010	10	160000	10	160000	50	1280000	1	1	5	160019	0	160038	160038	139986	0	3	140018	160010	20	160000	20	480000	160038	160038	1	1	160022	10	9	10	10	160000	10	0	0	0	0	0	10023	8	5	1	1	34	16	1	1	1	22	37	160033	21	17	160000	10	160039	160039	160039	160039	160039
160025	160038	1199	1	0	0	78	25	160010	10	160000	10	160000	50	1280000	1	1	5	160019	0	160038	160038	139986	0	3	140018	160010	20	160000	20	480000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10023	8	5	1	1	37	16	1	1	1	24	40	160033	21	17	160000	10	160039	160039	160039	160039	160085
160024	160038	1199	1	0	0	743	25	160010	10	160000	10	160000	50	1280000	1	1	5	160019	0	160038	160038	139986	0	3	140018	160010	20	160000	20	480000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10023	8	5	1	1	41	16	1	1	1	39	31	160033	21	17	160000	10	160087	160039	160039	160039	160039
160024	160038	1199	1	0	0	78	25	160010	10	160000	10	160000	50	1280000	1	1	5	160019	0	160038	160038	139986	0	3	140018	160010	20	160000	20	480000	160038	160038	1	1	160021	10	9	10	10	160000	10	1	0	0	0	0	10023	8	5	1	1	38	16	1	1	1	25	39	160033	21	17	160000	10	160039	160039	160039	160039	160039
160024	160038	1199	1	0	0	952	25	160010	10	160000	10	160000	50	1280000	1	1	5	160019	0	160038	160038	139986	3	3	140018	160010	20	160044	20	480000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10023	8	5	1	1	39	16	1	1	1	40	40	160033	21	17	160000	10	160039	160039	160039	160039	160039
160024	160038	1199	1	0	0	78	25	160010	10	160000	10	160000	50	1280000	1	1	5	160019	0	160038	160038	139986	0	3	140018	160010	20	160000	20	480000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10023	8	5	1	1	33	16	1	1	2	38	37	160033	21	17	160000	10	160039	160039	160039	160039	160039
160024	160038	1199	1	0	0	78	25	160010	10	160000	10	160000	50	1280000	1	1	5	160019	0	160038	160038	139986	0	3	140018	160010	20	160000	20	480000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10023	8	5	2	1	38	16	3	2	1	40	28	160033	21	33	160000	10	160039	160039	160039	160039	160233
160024	160038	1199	1	3	789	78	44	160058	10	160000	10	160000	50	1280000	1	1	5	160019	0	160038	160038	139986	0	3	140018	160010	20	160000	20	480000	160038	160038	1	1	160021	10	9	10	10	160000	10	0	3	0	0	0	10036	11	5	2	1	39	16	1	1	1	40	40	160255	21	17	160000	10	160039	160039	160039	160039	160039

SHA512SU1

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations