Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SHADD (vector, 16B)

Test 1: uops

Code:

  shadd v0.16b, v0.16b, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03091e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203716008216872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150012416872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715008416872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203716006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150022116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203716006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  shadd v0.16b, v0.16b, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
1020420037150008419687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100005071011611197910100001002003820038200382003820038
1020420037149008219687251010010010000100100005002847680120018200372003718422318745101002001018020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204200371500010319687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100200071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204200371500064119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100020071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
1002420037150010319687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
1002420037150012419687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
100242003715006119687251001010100001010000502847680120065200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
1002420037150012419687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100006402162219785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  shadd v0.16b, v1.16b, v0.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000061196872510100100100001001000050028476801200180200372003718422318745101002001000020020000200372003711102011009910010010000100000071021611197910100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476800200180200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820083
102042003715009061196872510100100100001001000050028476800200180200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
1020420037149027061196872510100100100001001000050028476800200180200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476800200180200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476800200180200372003718422318745101002001000020020000200372003711102011009910010010000100003079911611197910100001002003820038200382003820038
1020420085150012061196872510100100100001001000050028476800200180200372003718422318745101002001000020020000200372003711102011009910010010000100046071011611197910100001002003820038200382003820038
1020420037150015061196872510100100100001001000050028476800200180200372003718422318745101002001000020020000200372003711102011009910010010000100212000071011611197910100001002003820038200382003820038
10204200371500336061196872510100100100001001000050028476800200180200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715003061196872510100100100001001000050028476800200180200372003718422318745101002001000020020000200372003711102011009910010010000100010071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000000906119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000006403162219785010000102003820038200382003820038
1002420037150000001806119687251001010100001010000502847680200182003720037184447187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
1002420037150000002706119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
100242003715000000306119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
100242003715000000606119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
1002420037150000001506119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
100242003715000000306119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  shadd v0.16b, v8.16b, v9.16b
  shadd v1.16b, v8.16b, v9.16b
  shadd v2.16b, v8.16b, v9.16b
  shadd v3.16b, v8.16b, v9.16b
  shadd v4.16b, v8.16b, v9.16b
  shadd v5.16b, v8.16b, v9.16b
  shadd v6.16b, v8.16b, v9.16b
  shadd v7.16b, v8.16b, v9.16b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)18191e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420038155110012247258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100051148169920035800001002003920039200392003920039
802042003815011000247258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100051149164720035800001002003920039200392003920039
80204200381501100024725801001008000010080000500640000200192003820038997339996801002008000020016058220100200381180201100991001008000010005114101691020035800001002003920039200392003920039
8020420038150110024247258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100051145165920035800001002003920039200392003920039
8020420038150110012247258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100051141017101020035800001002003920039200392003920039
80204200381501100024725801001008000010080000500640000200192003820038997339996801002008000020016000020038200381180201100991001008000010005114816101020035800001002003920039200392003920039
8020420038150110002472580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000511491610920035800001002003920039200392003920039
802042003815011000247258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100051149169920035800001002003920039200392003920039
802042003815011006247258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100051149169920035800001002003920039200392003920039
802042003815011000247258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100051147169920035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)daddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004815000063039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000050207160352003580000102003920039200392003920039
80024200381490000039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000050205160462003580000102003920039200392003920039
80024200381500000039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000050203160352003580000102003920039200392003920039
80024200381500000039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000050203160352003580000102003920039200392003920039
80024200381500000039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000050205160562003580000102003920039200392003920039
80024200381500003039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000050203160352003580000102003920039200392003920039
80024200381500000039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000050205160572003580000102003920039200392003920039
80024200381500000039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000050205160532003580000102003920039200392003920039
800242003815000012039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000650203160552003580000102003920039200392003920039
800242003815000000392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010001250205160572003580000102003920039200392003920039