Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SHADD (vector, 8H)

Test 1: uops

Code:

  shadd v0.8h, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203716006116872510001000100026468002018203720371572318951000100020002037203711100110000073116121787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000673116121787100020382038203820382038
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000073116121787100020382038203820382038
10042037150216116872510001000100026468002018203720371572318951000100020002037203711100110001073116121787100020382038203820382038
1004203715066116872510001000100026468012018203720371572318951000100020002037203711100110004373116111787100020382038203820382038
10042037150061168725100010001000264680120182037203715723189510001000200020372037111001100003073116111787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000073116121787100020382038203820382038
1004203716006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000073116121787100020382038203820382038

Test 2: Latency 1->2

Code:

  shadd v0.8h, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150036119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100507101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018200372003718422318764101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150106119687251010010010000100100005002848963020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005162847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001005707101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820229

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150000000061196872510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000100010006402162219798010000102003820038200382003820038
1002420037150000000061196872510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000100000606402162219785010000102003820038200382003820038
1002420037150000000061196872510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
1002420037149000000061196872510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000100020606402162219785010000102003820038200382003820038
1002420037150000000061196872510010101000010100005028476801200180200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
1002420037150000000061196872510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
1002420037150000000061196872510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
1002420037150000000061196872510010101000010100005028476801200180200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
1002420037149000000061196872510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000100000306402162219785010000102003820038200382003820038
1002420037150000000061196872510010101000010100005028476800200180200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  shadd v0.8h, v1.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001003071011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476801200182008520037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
1020420037150361196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028482300200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010006403163319785010000102003820038200382003820038
10024200371501061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010006403163319785010000102003820038200382003820038
10024200371500061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010006403163319785010000102003820038200382003820038
10024200371500061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010580186403163319785010000102003820038200382003820038
10024200371500061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010006403163319785010000102003820038200382003820038
10024200371500061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010006403163319785010000102003820038200382003820038
10024200371500961196872510010101001210100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010036403163319853010000102003820038200382003820038
10024200371500061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010006403163319785010000102003820038200382003820038
10024200371500061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010136403163319785010000102003820038200382003820038
10024200371500061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010006403163319785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  shadd v0.8h, v8.8h, v9.8h
  shadd v1.8h, v8.8h, v9.8h
  shadd v2.8h, v8.8h, v9.8h
  shadd v3.8h, v8.8h, v9.8h
  shadd v4.8h, v8.8h, v9.8h
  shadd v5.8h, v8.8h, v9.8h
  shadd v6.8h, v8.8h, v9.8h
  shadd v7.8h, v8.8h, v9.8h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)0e191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200581500000040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000051102161120035800001002003920039200392003920039
80204200381500000040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039
802042003815000000103258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039
80204200381500000040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039
802042003815000000124258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000051281161120035800001002003920039200392003920039
802042003815000000103258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039
802042003815000000124258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100010051101161120035800001002003920039200392003920039
80204200381500000040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000351101161220035800001002003920039200392003920039
80204200381500000040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039
80204200381500000040258010010080000100800005006400002001920038200389973399968010020080000200160000200382003811802011009910010080000100000051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)033f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004815039258001010800001080000506400001200190200382003899967100448001020800002016000020038200381180021109101080000100005020216242003580000102003920039201112003920039
800242003815060258001010800001080000506400001200190200382003899963100188001020800002016000020038200381180021109101080000100005020416422003580000102003920039200392003920039
800242003815062258001010800001080000506400001200190200382003899963100188001020800002016000020038200381180021109101080000100005020416422003580000102003920039200392003920039
8002420038150324258001010800001080000506400001200190200382003899963100188001020800002016000020038200381180021109101080000100005020216242003580000102003920039200392003920039
800242003815039258001010800001080000506400001200190200382003899963100188001020800002016000020038200381180021109101080000102005020416422003580000102003920039200392003920039
800242003815039258001011800001380000506400001200190200382003899963100188001020800002016000020038200381180021109101080000100005020416422003580000102003920039200392003920039
800242003815081258001010800001080000506400001200190200382003899963100188001020800002016000020038200381180021109101080000100005020416262003580000102003920039200392003920039
800242003814939258001010800001080000506400001200190200382003899963100188001020800002016000020038200381180021109101080000101005020216422003780000102003920039200392003920039
800242003815081258001010800001080000506400001200190200382003899963100188001020800002016000020038200381180021109101080000100005020216242003580000102003920039200392003920039
800242003815039258001010800001080000506400001200190200382003899963100188001020800002016000020038200381180021109101080000100005020416442003580000102003920039200392003920039