Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SHLL2 (vector, 8H)

Test 1: uops

Code:

  shll2 v0.8h, v0.16b, #8
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)0309l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203715001561168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371500061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371500061168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371600061168625100010001000264521120182037203715713189510001000100020372037111001100001073116111786100020382038203820382038
100420371500061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371600061168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371501061168625100010001000264521120182037203715713189510001000100020372037111001100020073116111786100020382038203820382038
100420371500061168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371500061168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371500061168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  shll2 v0.8h, v0.16b, #8
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500000006119686251010010010000100100005002847521120018200372003718428618741101002001000820010008200372003711102011009910010010000100000000011171701600198010100001002003820038200382003820038
10204200371500000006119686251010010010000100100005002847521020018200372003718428618741101002001000820010008200372003711102011009910010010000100000002105011171701600198010100001002003820038200382003820038
10204200371500000006119686251010010010000100100005002847521120018200372003718428718740101002001000820010008200372003711102011009910010010000100000000011171801600198000100001002003820038200382003820038
10204200371500000006119686251010010010000100100005002847521120018200372003718428718741101002001000820010008200372003711102011009910010010000100000000000071011611197910100001002003820038200382003820038
10204200371500000006119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100000000000071011611197910100001002003820038200382003820038
10204200371500000008219686441010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100000000000071011611197910100001002003820038200382003820038
10204200371500000006119686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100000000000071011611197910100001002003820038200382003820038
10204200371500000006119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100000000000071011611197910100001002003820038200382003820038
102042003715000000053619686251010010010000100100005002847521120018200372003718421318745101002001000020010000200372003711102011009910010010000100000000000071011611197910100001002003820038200382003820038
10204200371500000006119686251010010010000100100005002847521020018200372003718421318745101002001000020010000200372003711102011009910010010000100000000000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acc2cfd2d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003718500000061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000006400216221978610000102003820038200382003820038
100242003718500000061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000006400216221978610000102003820038200382003820038
100242003718601000061196862510010101000010100005028475211200182003720037184433187671001020101632010168200372003711100211091010100001000006400216221978610000102003820038200382003820038
100242003717300000061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000006400216221978610000102003820038200382003820038
1002420037174000000124196862510010101000011101525028475210200182003720037184433187671001020100002010000200372003711100211091010100001000196006400416221978610000102003820038200382008520038
100242003717400000061196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000006400216221978610000102003820038200382003820038
100242003717300000061196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000006400216221978610000102003820038200382003820038
100242003716110000061196862510010101000010100005028475210200182003720037184433187671001020100002010000200372003711100211091010100001000006400216221978610000102003820038200382003820038
100242003716000000061196862510010101000010100005028475211200182003720037184433187671001020100002010000200842003711100211091010100001000006400216221978610000102003820038200382003820038
100242003716100000061196862510010101000010100005028475211200182003720037184433187671001020100002010000200372003711100211091010100001000006400216221978610000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  shll2 v0.8h, v8.16b, #8
  shll2 v1.8h, v8.16b, #8
  shll2 v2.8h, v8.16b, #8
  shll2 v3.8h, v8.16b, #8
  shll2 v4.8h, v8.16b, #8
  shll2 v5.8h, v8.16b, #8
  shll2 v6.8h, v8.16b, #8
  shll2 v7.8h, v8.16b, #8
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0318191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420057150000292580108100800081008002050064013220019200382003899776998980120200800322008003220038200381180201100991001008000010057311151182164420035800001002003920039200392003920039
802042003815000029258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001000011151183164320035800001002003920039200392003920039
80204200381500002925801081008000810080020500640132200192003820038997769989801202008003220080032200382003811802011009910010080000100014111151184164420035800001002003920039200392003920039
802042003815000629258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001000011151184164320035800001002003920039200392003920039
802042003815000029258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001000011151181163420035800001002003920039200392003920039
802042003815000029258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001000311151183163420035800001002003920039200392003920039
802042003815000029258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001000311151183164320035800001002003920039200392003920039
8020420038150000292580108100800081008002050064013220019200382003899776998980120200800322008003220038200381180201100991001008000010001811151184164520035800001002003920039200392003920039
802042003815000029258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001000011151184163420035800001002003920039200392003920039
802042003815000029258010810080008100800205006401322001920038200389977699898012020080032200800322003820038118020110099100100800001002011151183163320035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)dadbddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420050150000000039258001010800001080000506400000120019200382003899963100188001020800002080000200382003811800211091010800001000000005020316005320035080000102003920039200392003920039
80024200381500000000392580010108000010800005064000001200192003820038999631001880010208000020800002003820038118002110910108000010000004805020216002320035080000102003920039200392003920039
8002420038150000000039258001010800001080000506400000120019200382003899963100188001020800002080000200382003811800211091010800001000000305020516003220035080000102003920039200392003920039
8002420038150000000039258001010800001080000506400000120019200382003899963100188001020800002080000200382003811800211091010800001000000305020316003220035080000102003920039200392003920039
8002420038149000000060258001010800001080000506400001120019200382003899963100188001020800002080000200382003811800211091010800001000000005020216002320035080000102003920039200392003920039
80024200381500000000392580010108000010800005064000001200192003820038999631001880010208000020800002003820038118002110910108000010000001205020316002420035080000102003920039200392003920039
8002420038150000000039258001010800001080000506400000120019200382003899963100188001020800002080000200382003811800211091010800001000000005020316002320035080000102003920039200882003920039
8002420038150000000039258001010800001080000506400000120019200382003899963100188001020800002080000200382003811800211091010800001000000305020316003320035080000102003920039200392003920039
8002420038150000000039258001010800001080000506400000120019200382003899963100188001020800002080000200382003811800211091010800001000000005020516003220035080000102003920039200392003920039
8002420038150000000039258001010800001080000506400000120019200382003899963100188001020800002080000200382003811800211091010800001000000605020516003220035080000102003920039200392003920039