Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SHLL (vector, 2D)

Test 1: uops

Code:

  shll v0.2d, v0.2s, #32
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203715006116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715006116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715036116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715006116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715006116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
10042037150306116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715006116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715006116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715006116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715006116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  shll v0.2d, v0.2s, #32
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000054061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
102042003715003045061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
10204200371500000061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
102042003714900081061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
102042003715000045061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
102042003715000069061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
10204200371500006061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
102042003715000057061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
10204200371500003061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
102042003715000060061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)0f18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150000000780611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000000006404162219786010000102003820038200382003820038
100242003715000000000611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
100242003714900000000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
100242003715000000000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
100242003715000000000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
1002420037150000000270611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
1002420037150000000240611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000000006402172219786010000102003820038200382003820038
100242003715000000000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
10024200371500000002760611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
1002420037150000000120611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  shll v0.2d, v8.2s, #32
  shll v1.2d, v8.2s, #32
  shll v2.2d, v8.2s, #32
  shll v3.2d, v8.2s, #32
  shll v4.2d, v8.2s, #32
  shll v5.2d, v8.2s, #32
  shll v6.2d, v8.2s, #32
  shll v7.2d, v8.2s, #32
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042006115000060292580108100800081008002050064013220019200382003899776998980120200800322008003220038200381180201100991001008000010000000011151182162120035800001002003920039200392003920039
8020420038150000450292580108100800081008002050064013220019200382003899776998980120200800322008003220038200381180201100991001008000010000000011151181162220035800001002003920039200392003920039
802042003815000000292580108100800081008002050064013220019200382003899776998980120200800322008003220038200381180201100991001008000010000000011151181162220035800001002003920039200392003920039
8020420038150000120292580108100800081008002050064013220019200382003899776998980120200800322008003220038200381180201100991001008000010000000011151182162120035800001002003920039200392003920039
8020420038150000002925801081008000810080020500640132200192003820038997769989801202008003220080032200382003811802011009910010080000100000002411151182162220035800001002003920039200392003920039
8020420038150000210292580108100800081008002050064013220019200382003899776998980120200800322008003220038200381180201100991001008000010000000011151182162120035800001002003920039200392003920039
8020420038150000150292580108100800081008002050064013220019200382003899776998980120200800322008003220038200381180201100991001008000010000000011151182162120035800001002003920039200392003920039
802042003815000000292580108100800081008002050064013220019200382003899776998980120200800322008003220038200381180201100991001008000010001000011151181162120035800001002003920039200392003920039
802042003815000000292580108100800081008002050064013220019200382003899776998980120200800322008003220038200381180201100991001008000010000000011151181162120035800001002003920039200392003920039
8020420038150000120292580108100800081008002050064013220019200382003899776998980120200800322008003220038200381180201100991001008000010000000011151182162120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03181e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420050150069039258001010800001080000506400000020019200382003899960310018800102080000208000020038200381180021109101080000100000502015161782003580000102003920039200392003920039
80024200381500003925800101080000108000050640000002001920038200389996031001880010208000020800002003820038118002110910108000010004735020171617172003580000102003920039200392003920039
800242003815000039258001010800001080000506400000020019200382003899960310018800102080000208000020038200381180021109101080000100000502017166172003580000102003920039200392003920039
800242003815000039258001010800001080000506400000120019200382003899960310018800102080000208000020038200381180021109101080000100000502017166172003580000102003920039200392003920039
80024200381500003925800101080000108000050640000002001920038200389996031001880010208000020800002003820038118002110910108000010000050206166172003580000102003920039200392003920039
8002420038150460392580010108000010800005064000000200192003820038999603100188001020800002080000200382003811800211091010800001000005020171617172003580000102003920039200392003920039
8002420038150039039258001010800001080000506400000020019200382003899960310018800102080000208000020038200381180021109101080000100000502017166172003580000102003920039200392003920039
800242003815000039258001010800001080000506400000020019200382003899960310018800102080000208000020038200381180021109101080000100000502061617172003580000102003920039200392003920039
8002420038150015039258001010800001080000506400000020019200382003899960310018800102080000208000020038200381180021109101080000100000502017161762003580000102003920039200392003920039
800242003815000039258001010800001080000506400000020019200382003899960310018800102080000208000020038200381180021109101080000100000502017166172003580000102003920039200392003920039