Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SHLL (vector, 4S)

Test 1: uops

Code:

  shll v0.4s, v0.4h, #16
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)a9cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203715006116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715006116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715006116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715006116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715006116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203716006116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371501596116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203716006116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715006116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715006116862510001000100026452112018203720371571318951000100010002037203711100110000073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  shll v0.4s, v0.4h, #16
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fst unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150057061196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150000726196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042003715009061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000207101161119791100001002003820038200382003820038
1020420037150021061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
10204200371500177061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
1020420037150000536196862510100100100001001000050028475211200182003720037184213187451010020010000200100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038
102042008015000061196862510100100100001001000050028475210200182003720037184213187451010020010000200100002003720037111020110099100100100001000037101161119791100001002003820038200382003820038
102042008415000061196862510100100100001001000050028475210200182003720037184213187451010020010000204100002003720037111020110099100100100001000020107101161119791100001002003820038200382003820038
1020420037150093061196862510100100100001001000050028475210200182003720037184213187451010020010000204100002003720037111020110099100100100001000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500000000611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
10024200371500000000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
10024200371500000000611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
10024200371500000000611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
10024200371500000000841968625100101010000101000050284752112005420037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
10024200371500000000611968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
1002420037150000024007261968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
10024200371500000000611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
1002420037150000027001031968625100101010000101000050284752112001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038
1002420037150000021600611968625100101010000101000050284752102001820037200371844331876710010201000020100002003720037111002110910101000010000000006402162219786010000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  shll v0.4s, v8.4h, #16
  shll v1.4s, v8.4h, #16
  shll v2.4s, v8.4h, #16
  shll v3.4s, v8.4h, #16
  shll v4.4s, v8.4h, #16
  shll v5.4s, v8.4h, #16
  shll v6.4s, v8.4h, #16
  shll v7.4s, v8.4h, #16
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9facbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420060150122925801081008000810080020500640132200822003820038997769989801202008003220080032200382003811802011009910010080000100011151180160020035800001002003920039200392003920039
8020420038150050425801081008000810080020500640132200192003820038997769989801202008003220080032200382003811802011009910010080000100011151180160020035800001002003920039200392003920039
8020420038150242925801081008000810080020500640132200192003820038997769989801202008003220080032200382003811802011009910010080000100011151181160020035800001002003920039200392003920039
8020420038150212925801081008000810080020500640132200192003820038997769989801202008003220080032200382003811802011009910010080000100011151181160120035800001002003920039200392003920039
8020420038150722925801081008000810080020500640132200192003820038997769989801202008003220080032200382003811802011009910010080000100011151180160020035800001002003920039200392003920039
802042003815002925801081008000810080020500640132200192003820038997769989801202008003220080032200382003811802011009910010080000100011151180160020035800001002003920039200392003920039
802042003815062925801081008000810080020500640132200192003820038997769989801202008003220080032200382003811802011009910010080000100011151180160020035800001002003920039200392003920039
8020420038150152925801081008000810080020500640132200192003820038997769989801202008003220080032200382003811802011009910010080000100011151180160020035800001002003920039200392003920039
802042003815032925801081008000810080020500640132200192003820038997769989801202008003220080032200382003811802011009910010080000100011151180160020035800001002003920039200392003920039
802042003815032925801081008000810080020500640132200192003820038997769989801202008003220080032200382003811802011009910010080000100011151181160020035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200391500000039258001010800001080000506400001200192003820038999631001880010208000020800002003820038118002110910108000010000502015161772003580000102003920039200392003920039
80024200381500000039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010000502017168172003580000102003920039200392003920039
800242003815000023703925800101080000108000050640000120019200382003899963100188001020800002080000200382003811800211091010800001000050208168172003580000102003920039200392003920039
8002420038150000930392580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100005020151617172003580000102003920039200392003920039
80024200381490000032425800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001000050206168172003580000102003920039200392003920039
80024200381500001203925800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001000050206161762003580000102003920039200392003920039
80024200381500000039258001010800001080000506400000200192003820038999631001880010208000020800002003820092118002110910108000010000502017168172003580000102003920039200392003920039
80024200381500000039258001010800001080112506400000200192003820038999631001880010208000020800002003820038118002110910108000010109502017161472003580000102003920039200392003920039
800242003815000024039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010100502017161562003580000102003920039200392003920039
800242003815000087039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010000502017161762003580000102003920039200392003920039