Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SHL (vector, 16B)

Test 1: uops

Code:

  shl v0.16b, v0.16b, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)091e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371500061168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371500061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371500061168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371500061168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
1004203715000103168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371510361168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371500061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371500061168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371600061168625100010001000264521020182037203715713189510001000100020372037111001100000073116111786100020382038203820382038
100420371501061168625100010001000264521120182037203715713189510001000100020372037111001100000073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  shl v0.16b, v0.16b, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042003715000611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000067101161119791100001002003820038200382003820038
102042003715000611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010001801057101161119791100001002003820038200382003820038
102042003715000611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010004007101161119791100001002003820038200382003820038
102042003715000611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010007007101161119791100001002003820038200382003820038
10204200371500012031968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010006007101161119791100001002003820038200382003820038
102042003715000611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000037101161119791100001002003820038200382003820038
102042003715000611968625101001001000010010000500284752102001820037200371842131874510100200100002001000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042003715000611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000007101160119791100001002003820038200382003820038
102042003715000611968625101001001000010010000500284752112001820037200371842131874510100200100002001000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500006119686251001010100001010000502847521200182003720037184430318767100102010000201000020037200371110021109101010000100000640416221978610000102003820038200382003820038
100242003715009044119686251001010100001010000502847521200182003720037184430318767100102010000201000020037200371110021109101010000100200640216221978610000102003820038200382003820038
10024200371500006119686251001010100001010000502847521200182003720037184430318767100102010000201000020037200371110021109101010000100101805640216521978610000102003820038200382003820038
10024200371500006119686251001010100001010000502847521200182003720037184430318767100102010000201000020037200371110021109101010000100000640216221978610000102003820038200382003820038
10024200371500006119686251001010100001010000502847521200182003720037184430318767100102010000201000020037200371110021109101010000104000640217221978610000102003820038200382003820038
100242003715000044119686251001010100001010000502847521200182003720037184430318767100102010000201000020037200371110021109101010000100000640216221978610000102003820038200382003820038
10024200371500006119686251001010100001010000502847521200182003720037184430318767100102010000201000020037200371110021109101010000100000640216221978610000102003820038200382003820038
10024200371500006119686251001010100001010000502847521200182003720037184430318767100102010000201000020037200371110021109101010000100000640216221978610000102003820038200382003820038
10024200371500006119686251001010100001010000502847521200182003720037184430318767100102010000201000020037200371110021109101010000100000640216221978610000102008520038200382003820038
100242003715000061196862510010101000010100005028475212001820037200371844303187671001020100002010000200372003711100211091010100001003500640216221978610000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  shl v0.16b, v8.16b, #3
  shl v1.16b, v8.16b, #3
  shl v2.16b, v8.16b, #3
  shl v3.16b, v8.16b, #3
  shl v4.16b, v8.16b, #3
  shl v5.16b, v8.16b, #3
  shl v6.16b, v8.16b, #3
  shl v7.16b, v8.16b, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200571501100942580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000011151181161120035800001002003920039200392003920039
80204200381501100292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000011151181161120035800001002003920039200392003920039
80204200381501100292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000011151181161120035800001002003920039200392003920039
80204200381501100702580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001001011151181161120035800001002003920039200392003920039
802042003815011005922580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000011151181161120035800001002003920039200392003920039
80204200381501100292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000011151181161120035800001002003920039200392003920039
802042003815011004092580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000011151181161120035800001002003920039200392003920039
80204200381501100292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000011151181161120035800001002003920039200392003920039
80204200381501100292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000311151181161120035800001002003920106200392003920039
80204200381501100292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000011151181161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200501500000000003925800101080000108000050640000020019200382003899963100188001020800002080000200382003811800211091010800001000000005020616292003580000102003920039200392003920039
8002420038150000000000392580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100000000502015163152003580000102003920039200392003920039
8002420038150000000000392580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100000000502015161562003580000102003920039200392003920039
8002420038150000000000392580010108000010800005064000012001920038200389996310018800102080000208000020038200381180021109101080000100000000502051613152003580000102003920039200392003920039
8002420038150000000000392580010108000010800006064000002001920038200389996310018800102080000208000020038200381180021109101080000100000000502015164152003580000102011020039201112019020039
8002420038150000000000392580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100000000502015161242003580000102003920039200392003920039
8002420038150000000000392580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100000000502015161552003580000102003920039200392003920039
800242003815000000023100392580090108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100000000502015165102003580000102003920039200392003920039
800242003815000000000039258001010800001080000506400000200192003820038999631001880010208000020800002003820038118002110910108000010000000050205165152003580000102003920039200392003920039
800242003814900000015001442580010108000010800005064000002001920038200389996310018800102080000208000020038200381180021109101080000100200000502051615152003580000102003920039200392003920039