Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SHL (vector, 4H)

Test 1: uops

Code:

  shl v0.4h, v0.4h, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371506116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371506116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371506116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371506116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715010216862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371506116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371506116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371506116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
1004203715040816862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038
100420371506116862510001000100026452102018203720371571318951000100010002037203711100110000073116111786100020382038203820382038

Test 2: Latency 1->2

Code:

  shl v0.4h, v0.4h, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)0918191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fst unit uop (a7)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000000061196862510100100100001001000050028475212001820037200371842861874110100200100082001000820037200371110201100991001001000010000011171701600198000100001002003820038200382003820038
1020420037150000000658196862510100100100001001000050028475212001820037200371842871874010100200100082001000820037200371110201100991001001000010000011171701600198010100001002003820038200382003820038
102042003715000000061196862510100100100001001000050028475212001820037200371842131874510100200100002001000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
102042003715000000061196862510100100100001001000050028475212001820037200371842131874510100200100002001000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
102042003715000000084196862510100100100001001000050028475212001820037200371842131874510100200100002001000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
102042003715500000061196862510100100100001001000050028475212001820037200371842131874510100200100002001000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
102042003715000000061196862510100100100001001000050028475212001820037200371842131874510100200100002001000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
1020420037150000012061196862510100100100001001000050028475212005420037200371842131874510100200100002001000020037200371110201100991001001000010000000071011611197910100001002003820086200382003820038
102042003715000000061196862510100100100001001000050028475212005420037200371842131874510100200100002001000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
10204200371500000088156196862510100100100001001015250028475212001820037200371842131874510100200100002001000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100640316221978610000102003820038200382003820038
100242003715006119686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
100242003715006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200375110021109101010000100640216221978610000102003820038200382003820038
1002420037150072619686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
100242003715006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
100242003715006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
100242003715006119686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
100242003715006119686251001010100001010000502847521020018200372003718443318767100102010000201000020037200851110021109101010000100640216221978610000102003820038200382003820038
100242003715006119686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100640216221978610000102003820038200382003820038
1002420037150093319686251001010100001010000502847521120018200372003718443318767100102010000201000020037200371110021109101010000100640316221978610000102003820038200382003820038

Test 3: throughput

Count: 8

Code:

  shl v0.4h, v8.4h, #3
  shl v1.4h, v8.4h, #3
  shl v2.4h, v8.4h, #3
  shl v3.4h, v8.4h, #3
  shl v4.4h, v8.4h, #3
  shl v5.4h, v8.4h, #3
  shl v6.4h, v8.4h, #3
  shl v7.4h, v8.4h, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)181e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042006115000000292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000000111511811620035800001002003920039200392003920039
802042003815000000292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000000111511801620035800001002003920039200392003920039
802042003815000000712580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000000111511801620035800001002003920039200392003920039
8020420038150000009002580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000000111511801620035800001002003920039200392003920039
802042003815000100292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000000111511801620035800001002003920039200392003920039
802042003815000000292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000000111511801620035800001002003920039200392003920039
802042003815000000292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000000111511811620035800001002003920039200392003920039
802042003815000000292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000000111511801620105800001002003920039200392003920039
802042003815000000292580108100800081008002050064013212001920038200389977699898012020080032200800322003820038118020110099100100800001000000111511801620035800001002003920039200392003920039
802042003815000000292580108100800081008002050064013202001920038200389977699898012020080032200800322003820038118020110099100100800001000000111511801620035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242005015003925800101080000108000050640000120019020038200389996310018800102080000208000020038200381180021109101080000100005020017166132003580000102003920039200392003920039
800242003815003925800101080000108000050640000020019020038200389996310018800102080000208000020038200381180021109101080000100005020013161662003580000102003920039200392003920039
80024200381500602580010108000010800005064000012001902003820038999631001880010208000020800002003820038118002110910108000010000502006166132003580000102003920039200392003920039
80024200381500392580010108000010800005064000002001902003820038999631001880010208000020800002003820038118002110910108000010000502005166162003580000102003920039200392003920039
80024200381500735258001010800001080000506400000200190200382003899963100188001020800002080000200382003811800211091010800001000050200161616162003580000102003920039200392003920039
800242003815003925800101080000108000050640000020019020038200389996310018800102080000208000020038200381180021109101080000100005020016166162003580000102003920039200392003920039
800242003815007102580010108000010800005064000002001902003820038999631001880010208000020800002003820038118002110910108000010000502006161662003580000102003920039200392003920039
8002420038150069925800101080000108000050640000120019020038200389996310018800102080000208000020038200381180021109101080000100005020010161662003580000102003920039200392003920039
800242003815003925800101080000108000050640000120019020038200389996310018800102080000208000020038200381180021109101080000100005020014166162003580000102003920039200392003920039
8002420038150039258001010800001080000506400000200190200382003899963100188001020800002080000200382003841800211091010800001000050200141616162003580000102003920039200392003920039