Firestorm: SHRN2 (8H) measurements

Code:

  shrn2 v0.16b, v1.8h, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  shrn2 v0.16b, v1.8h, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	76	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	105	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20990	30086	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30084	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	0	0	0	61	29548	25	10010	10	10000	12	10000	50	4277313	0	30018	30037	30037	28287	0	3	28767	10012	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	642	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	536	29548	25	10010	10	10000	10	10000	55	4277313	1	30018	30037	30037	28287	0	3	28767	10010	20	10652	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	0	0	61	29548	25	10017	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	0	3	28767	10012	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	0	3	28767	10012	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	2	10000	10	30038	30038	30038	30038	30038
10024	30037	224	1	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	3	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	0	3	28767	10010	20	10179	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	441	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  shrn2 v0.16b, v0.8h, #3

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28271	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	717	16	29646	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10202	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	717	16	29646	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28271	7	28740	10100	200	10008	200	20016	30084	30037	1	1	10201	100	99	100	100	10000	100	0	2	0	0	0	1	1	1	717	16	29646	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28271	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	717	16	29645	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28271	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	718	16	29645	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28271	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	4	0	3	1	1	1	717	16	29645	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28271	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	717	16	29646	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	717	16	29646	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	718	16	29645	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	1	1	1	717	16	29646	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	2	0	0	640	3	16	3	3	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	24	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	82	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	15	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28291	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	3	16	3	3	29629	10000	10	30038	30038	30038	30038	30038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  shrn2 v0.16b, v8.8h, #3
  movi v1.16b, 0
  shrn2 v1.16b, v8.8h, #3
  movi v2.16b, 0
  shrn2 v2.16b, v8.8h, #3
  movi v3.16b, 0
  shrn2 v3.16b, v8.8h, #3
  movi v4.16b, 0
  shrn2 v4.16b, v8.8h, #3
  movi v5.16b, 0
  shrn2 v5.16b, v8.8h, #3
  movi v6.16b, 0
  shrn2 v6.16b, v8.8h, #3
  movi v7.16b, 0
  shrn2 v7.16b, v8.8h, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20088	150	0	0	48	0	29	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10119	0	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10119	0	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	21	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10119	0	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	36	0	29	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10119	0	16	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	33	0	29	25	80116	100	80016	100	80028	500	640196	0	20045	20065	20065	14	79	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10119	0	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	12	598	29	90	80224	100	80124	100	80132	500	640196	1	20045	20147	20147	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10119	0	16	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	15	0	29	321	80223	100	80016	100	80028	505	641044	0	20045	20147	20147	6	12	80128	200	80028	200	160056	20065	20147	1	1	160201	100	99	100	100	160000	100	4	0	0	2	530	0	1	1	1	10119	0	16	0	20062	160000	100	20458	20164	20066	20115	20199
160204	20065	150	1	1	6	0	29	25	80116	100	80016	100	80239	500	641052	0	20045	20065	20065	6	12	80233	200	80240	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	4	0	0	0	0	0	1	1	1	10143	0	16	0	20062	160000	100	20066	20149	20066	20066	20066
160204	20065	151	0	2	0	0	504	87	80221	100	80112	100	80133	500	641036	1	20118	20154	20155	13	12	80128	202	80136	202	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	0	3	0	1	1	1	10119	1	182	3	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	6	0	71	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10119	0	16	0	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20076	150	6	0	425	25	80010	10	80000	10	80000	50	640000	1	1	20042	0	20046	20046	3	22	80010	20	80000	20	160000	20048	20048	1	1	160021	10	9	10	10	160000	10	0	10048	3	1	1	25	20	1	1	1	18	21	20043	15	160000	10	20047	20049	20153	20049	20049
160024	20048	150	6	0	45	25	80010	10	80000	10	80000	50	640000	1	1	20038	0	20046	20046	3	22	80010	20	80000	20	160000	20046	20050	1	1	160021	10	9	10	10	160000	10	1	10043	6	1	1	18	20	4	1	1	18	18	20045	15	160000	10	20049	20049	20047	20047	20053
160024	20046	151	21	0	45	25	80010	10	80000	10	80000	50	640000	1	1	20047	0	20046	20050	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	10045	3	1	1	23	22	2	1	1	23	18	20043	31	160000	10	20047	20047	20047	20047	20047
160024	20050	150	0	0	45	25	80010	10	80000	10	80000	50	640000	1	1	20047	0	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	10042	3	2	1	19	20	2	1	2	20	16	20045	15	160000	10	20049	20047	20047	20049	20049
160024	20046	150	48	0	73	25	80010	10	80000	10	80000	50	640000	1	1	20038	0	20046	20046	3	22	80010	20	80000	20	160000	20048	20048	1	1	160021	10	9	10	10	160000	10	0	10042	3	1	1	20	26	1	1	1	20	19	20045	15	160000	10	20049	20051	20047	20047	20047
160024	20050	150	342	0	45	25	80010	10	80000	10	80000	50	640000	1	1	20039	0	20046	20048	3	22	80010	20	80000	20	160000	20050	20046	1	1	160021	10	9	10	10	160000	10	0	10040	3	1	1	19	20	1	1	1	18	18	20045	16	160000	10	20047	20047	20047	20047	20138
160024	20048	150	0	0	45	25	80010	10	80000	10	80000	50	640000	1	1	20039	0	20046	20048	3	22	80010	20	80000	20	160000	20050	20048	1	1	160021	10	9	10	10	160000	10	0	10045	3	1	1	23	22	2	2	1	19	22	20043	30	160000	10	20053	20047	20051	20047	20047
160024	20048	150	0	0	45	25	80010	10	80000	10	80000	50	640000	1	1	20037	0	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	10040	3	1	1	17	24	2	1	1	21	17	20043	16	160000	10	20047	20049	20053	20047	20047
160024	20048	150	12	0	45	25	80010	10	80000	10	80000	50	640000	1	1	20037	0	20048	20048	3	22	80010	20	80000	20	160000	20048	20048	1	1	160021	10	9	10	10	160000	10	0	10043	3	1	1	18	20	2	1	1	21	22	20043	16	160000	10	20047	20049	20049	20049	20047
160024	20046	150	0	0	45	25	80010	10	80000	10	80000	50	640000	0	1	20046	0	20046	20046	3	22	80010	20	80000	20	160000	20046	20048	1	1	160021	10	9	10	10	160000	10	0	10043	6	1	1	19	22	4	1	1	20	23	20043	15	160000	10	20047	20047	20049	20049	20049

Test 5: throughput

Count: 16

Code:

  shrn2 v0.16b, v16.8h, #3
  shrn2 v1.16b, v16.8h, #3
  shrn2 v2.16b, v16.8h, #3
  shrn2 v3.16b, v16.8h, #3
  shrn2 v4.16b, v16.8h, #3
  shrn2 v5.16b, v16.8h, #3
  shrn2 v6.16b, v16.8h, #3
  shrn2 v7.16b, v16.8h, #3
  shrn2 v8.16b, v16.8h, #3
  shrn2 v9.16b, v16.8h, #3
  shrn2 v10.16b, v16.8h, #3
  shrn2 v11.16b, v16.8h, #3
  shrn2 v12.16b, v16.8h, #3
  shrn2 v13.16b, v16.8h, #3
  shrn2 v14.16b, v16.8h, #3
  shrn2 v15.16b, v16.8h, #3

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40058	300	0	30	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	0	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40089	40040	40040	40040	40040
160204	40039	299	0	30	25	160108	100	160008	100	160020	500	1280132	0	40061	40039	40039	19977	0	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	30	25	160108	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	0	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	30	25	160108	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	0	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	299	0	30	25	160108	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	0	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	30	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	0	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	30	25	160108	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	0	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	299	0	30	25	160108	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	0	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	30	25	160108	100	160008	100	160020	500	1280132	1	40020	40039	40039	19977	0	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	300	0	30	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	0	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	91	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40051	299	0	0	0	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	5	40020	0	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	0	10	10	160000	10	0	0	0	0	0	10022	11	2	1	6	16	2	1	2	7	6	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	5	40020	0	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	0	10	10	160000	10	0	0	0	0	0	10022	8	3	1	7	16	2	1	1	7	7	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	5	40020	0	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	0	10	10	160000	10	0	0	0	0	0	10022	8	2	2	7	16	2	1	2	4	6	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	0	1	5	40020	0	40039	40039	19996	8	20019	160010	20	160000	20	320210	40039	40130	1	1	160021	10	9	0	10	10	160000	10	0	0	0	0	0	10022	8	2	1	4	16	2	1	1	4	4	40036	15	6	160000	10	40104	40040	40040	40040	40040
160024	40039	300	1	0	0	0	0	0	94	25	160010	10	160000	10	160000	50	1280000	0	1	5	40020	0	40039	40039	19996	3	20048	160010	20	160000	20	320636	40091	40039	1	1	160021	10	9	0	10	10	160000	10	0	0	0	0	0	10022	8	2	1	7	16	2	1	1	4	4	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	299	0	0	0	0	0	0	521	25	160010	10	160000	10	160000	50	1280000	1	1	5	40020	0	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	0	10	10	160000	10	0	0	0	0	0	10022	8	2	1	4	16	2	1	1	4	3	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	5	40020	0	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	0	10	10	160000	10	0	0	0	0	0	10022	8	2	1	4	36	2	1	1	6	6	40036	15	5	160000	10	40102	40040	40040	40040	40040
160024	40039	300	0	11	10	1332	968	1	46	25	160010	10	160000	10	160000	50	1280000	1	1	5	40315	0	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	0	10	10	160000	10	0	2	0	3	0	10022	8	2	1	3	16	2	1	1	6	4	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	299	0	0	0	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	5	40020	0	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	0	10	10	160000	10	0	0	1	0	0	10022	8	2	1	3	16	2	1	1	4	4	40036	15	5	160000	10	40040	40040	40040	40250	40040
160024	40039	300	0	0	0	12	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	5	40020	0	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	0	10	10	160000	10	0	0	0	0	0	10022	8	2	1	4	16	2	1	1	4	3	40036	30	5	160000	10	40040	40040	40040	40040	40040

SHRN2 (8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations