Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SHRN (8H)

Test 1: uops

Code:

  shrn v0.8b, v0.8h, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303723061254725100010001000398160301830373037241432895100010001000303730371110011000073316332629100030383038303830383038
10043037221261254725100010001000398160301830373037241432895100010001000303730371110011000373316332629100030383038303830383038
10043037230156254725100010001000398160301830373037241432895100010001000303730371110011000073316332629100030383038303830383038
1004303722061254725100010001000398160301830373037241432895100010001000303730371110011000073316332629100030383038303830383038
1004307322061254725100010001000398160301830373037241432895100010001000303730371110011000073316332629100030383038303830383038
1004303722201346254725100010001000398160301830373084241432895100010001000303730371110011000073316332629100030383038303830383038
1004303722061254725100010001000398160301830373037241432895100010001000303730371110011000073316332629100030383038303830383038
1004303723061254725100010001000398160301830373037241432895100010001000303730371110011000073316332629100030383038303830383038
1004303722061254725100010001000398160301830373037241432895100010001000303730371110011000088316332629100030383038303830383038
1004303723061254725100010001000398160301830373037241432895100010001000303730371110011000073316332629100030383038303830383038

Test 2: Latency 1->2

Code:

  shrn v0.8b, v0.8h, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225001262954725101001001000010010000500427716003001803003730037282643287451010020010000200100003003730037111020110099100100100001000000000710011611296330100001003003830038300383003830038
1020430037225001912954725101001001000010010000500427716003001803003730037282643287451010020010000200100003003730037111020110099100100100001000000000710011611296330100001003003830038300383003830038
1020430037225001892954725101001001000010010000500427716003001803003730037282643287451010020010000200100003003730037111020110099100100100001000000000710011611296330100001003003830038300383003830038
1020430037225001892954725101001001000010010000500427716003001803003730037282643287451010020010000200100003003730037111020110099100100100001000000000710011611296330100001003003830038300383003830038
1020430037224001262954725101001001000010010000500427716003001803003730037282643287451010020010000200100003003730037111020110099100100100001000000000710011611296330100001003003830038300863008630038
1020430037225008292954725101001001000010010000500427716003001803003730037282643287451010020010000200100003003730037111020110099100100100001000000000710011611296330100001003003830038300383003830038
1020430037224001262954725101001001000010010000500427716003001803003730037282643287451010020010000200100003003730037111020110099100100100001000000000710011611296330100001003003830038300383003830038
102043003722500822954725101001001000010010000500427716003001803003730037282643287451010020010000200100003003730037111020110099100100100001000000000710011611296330100001003003830038300383003830038
1020430037225001032954725101001001000010010000500427716003001803003730037282643287451010020210000200100003003730037111020110099100100100001000000000710011611296330100001003003830038300383003830038
1020430037225001032954725101001001000010010000500427716003001803003730037282643287451010020010000200100003003730037111020110099100100100001000000300710011611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000900210295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000000006405165629629110000103003830038300383003830038
1002430037225000000822954725100181010000101000050427716003001830133301782829920288171046322104842210659301323017841100211091010100001000000006406166729629010000103003830038300383003830038
100243003722500000061295472510010101000010100005042771600300183003730037282863287861001020100002010000300373003711100211091010100001000000606406166629629010000103003830038300383003830038
1002430037225000000124295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000000006407166729629010000103003830038300383003830038
100243003722500013588061295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000000006406166629629010000103003830038300383003830038
100243003722500000061295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000000006407167629629010000103003830038300383003830038
1002430037224000000107295472510010101000010100005042771601300183003730037282863287671001020100002010000300373003711100211091010100001000000006406167629629010000103003830038300383003830038
1002430037225000000612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000520306406167629629010000103003830038300383003830038
1002430037225000000214295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000000906407166729629010000103003830038300383003830038
1002430037225000000823295472510010101000010100005042771601300183008430084282866287901001020100002010000300373003711100211091010100001000000006407167629629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  shrn v0.8b, v8.8h, #3
  shrn v1.8b, v8.8h, #3
  shrn v2.8b, v8.8h, #3
  shrn v3.8b, v8.8h, #3
  shrn v4.8b, v8.8h, #3
  shrn v5.8b, v8.8h, #3
  shrn v6.8b, v8.8h, #3
  shrn v7.8b, v8.8h, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss data (0b)0e1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fst unit uop (a7)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200591500000030258010810080008100800205006401321020020200392003999776999080120200800322008003220039200391180201100991001008000010000001115118000160020036800001002004020040200402004020040
80204200391500000030258020810080008100800205006401320020020200392003999776999080120200800322008003220039200391180201100991001008000010000001115118000160020036800001002004020040200402004020040
80204200391500000030258010810080008100800205006401321020020200392003999776999080120200800322008003220039200391180201100991001008000010000001115118000160020036800001002004020040200402004020040
80204200391500000074258010810080008100800205006401321020020200392003999776999080120200800322008003220039200391180201100991001008000010000001115118000160020036800001002004020040200402004020040
80204200391500000030258010810080008100800205006401320020020200392003999776999080120200800322008003220039200391180201100991001008000010000001115118000160020036800001002004020040200402004020040
80204200391500000030258010810080008100800205006401320020020200392003999776999080120200800322008003220039200391180201100991001008000010000001115118000160020036800001002004020040200402004020040
80204200391502010030258010810080212100800205006401321020020200392003999776999080120200800322008003220039200391180201100991001008000010000001115118000160020036800001002004020040200402004020040
80204200391500000030258010810080008100800205006401321020020200392003999776999080120200800322008003220039200391180201100991001008000010001001115118000160020036800001002004020040200402004020040
80204200391500000030258010810080008100800205006401321020020200392003999769998680128200800382008003820048200491180201100991001008000010000002225128001231120045800001002004920049200492004920050
802042004915000000106268011610080016100800285006401960020029200482004999766999080120200800322008003220039200391180201100991001008000010000001115118000160020036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acbranch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242005115000402580010108000010800005064000001200202003920039999631001980010208000020800002003920039118002110910108000010000005020216112003680000102004020040200402004020040
800242003915000402580010108000010800005064000001200202003920039999631001980010208000020800002003920039118002110910108000010000005020116112003680000102004020040200402004020040
800242003915000402580010108000010800005064000001200202003920039999631001980010208000020800002003920039118002110910108000010200005020116112003680000102004020040200402004020040
800242003915000402580010108000010800005064000010200202003920039999631001980010208000020800002003920039118002110910108000010000005020116112003680000102004020040200402004020040
800242003915000402580010108000010800005064000000200202003920039999631001980010208000020800002003920039118002110910108000010000005020116112003680000102004020040200402004020040
800242003915000402580010108000010800005064000000200202003920039999631001980010208000020800002003920039118002110910108000010030005020116112003680000102004020040200402004020040
800242003915000402580010108000010800005064000001200202003920039999631001980010208000020800002003920039118002110910108000010000005020216222003680000102004020040200402004020040
800242003915000402580010108000010800005064000001200202003920039999631001980010208000020800002003920039118002110910108000010000005020216112003680000102004020040200402004020040
800242003915000402580010108000010800005064000001200202003920039999631001980010208000020800002003920039118002110910108000010000015020216222003680000102004020040200402004020040
800242003915000405080010108000010800005064000000200202003920039999631001980010208000020800002003920039118002110910108000010000005020116112003680000102004020040200402004020040