Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SHSUB (vector, 16B)

Test 1: uops

Code:

  shsub v0.16b, v0.16b, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371506116872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371506116872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371506116872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371506116872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371608416872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371506116872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371506116872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371506116872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371506116872510001000100026468020182037203715723189510001000200020372037111001100000073116111787100020382038203820382038
100420371506116872510001000100026468020182037203715723189510001000200020372037111001100000673116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  shsub v0.16b, v0.16b, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9facbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100007102161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715003611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042008415000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150007261968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000106640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018200372022618444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
10024200371500103196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001021640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
100242003715008219667251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
1002420037150072619687251001010100001010000502847680120018200372022718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  shsub v0.16b, v1.16b, v0.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150000006119687251010010010000100100005002847680120018020037200371842231874510100200100002002000020037200371110201100991001001000010001071011611197910100001002003820038200382003820038
1020420037150000006119687251010010010000100100005002847680120018020037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037150000006119687251010010010000100100005002847680120018020037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382008520038
10204200371500000034619687251010010010000100100005002847680120018020037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200872008720038
102042003715500000114819687251010010010000100100005002847680120018020037200371842231874510100200100002002000020037200371110201100991001001000010001071011611197910100001002003820038200382003820038
1020420037150000006119687251010010010000100100005002847680120018020037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037150000006119687251010010010000100100005002847680120018020037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037150000006119687251010010010000100100005002847680120018020037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037150000006119687251010010010000100100005002847680120018020037200371842231874510100200100002002000020037200371110201100991001001000010000371011611197910100001002003820038201792003820038
1020420037149000006119687251010010010000100100005002847680120018020037200371842231874510100200100002042000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150000000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006403164319785010000102003820038200382003820038
10024200371500000000089519687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000006402163419785010000102003820038200382003820038
10024200371500000000056719687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006403163319785010000102003820038200382003820038
10024200371500000000036019687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000006403163319785010000102003820038200382003820038
10024200371500000000045019687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000006403163319785210000102003820038200382003820038
1002420037150000000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006403163319785010000102003820038200382003820038
1002420037150000000006119687251001010100001010000502847680120018200372003718444618767100102010000202000020037200371110021109101010000100001306403163319785010000102003820038200382003820038
10024200371501000009906119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000306403163319785010000102003820038200382003820038
10024200371500000001808419687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006403163319785010000102003820038200382003820038
1002420037150000000008219687251001010100001010000502847680120018200372003718444318767100102210000202000020037200371110021109101010000100001006403163319785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  shsub v0.16b, v8.16b, v9.16b
  shsub v1.16b, v8.16b, v9.16b
  shsub v2.16b, v8.16b, v9.16b
  shsub v3.16b, v8.16b, v9.16b
  shsub v4.16b, v8.16b, v9.16b
  shsub v5.16b, v8.16b, v9.16b
  shsub v6.16b, v8.16b, v9.16b
  shsub v7.16b, v8.16b, v9.16b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)09l2 tlb miss instruction (0a)181e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042003815010100022232580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000511491677200350800001002003920039200392003920039
802042003815010110024725801001008000010080000500640000020019200382003899732099968010020080000200160000200382003811802011009910010080000100000511441699200358800001002014020529202462013820281
80204200381501010002472580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000511491677200350800001002003920039200392003920039
802042003815010101202472580100100800001008000050064000002001920038200389973399968010020080000200160198200382003811802011009910010080000100000511491699200350800001002003920039200392003920039
80204200381501010002472580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000511491699200350800001002003920039200392003920039
80204200381501010002472580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100031498511493249200350800001002003920039200392003920039
80204200381501110002472580100100800001008000050064076402001920038200389973399968010020080000200160000200382003811802011009910010080000100003511491699200350800001002003920039200392003920039
80204200381501010002472580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000511441699200350800001002003920039200392003920039
80204200381501010002472580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000511491699200350800001002003920039200392003920039
80204200381501010002472580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100000511491699200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242003915100392580010108000010800005064000004200192003820038999631001880010208000020160000200382003811800211091010800001000502005162220035080000102003920039200392003920039
800242003815000452580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000502004162220035080000102003920039200392003920039
800242003815000392580010108000011800005664000000200192003820038999631001880010208000020160000200382003811800211091010800001000502003162220035080000102003920039200392003920039
800242003815000392580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000502004162220035080000102003920039200392003920039
800242003815000392580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000502004162220035080000102003920039200392003920039
800242003815000392580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000502004162220035080000102003920039200392003920039
800242003815000392580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000502003162220035080000102003920039200392003920039
800242003815010392580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000502004163320035080000102003920039200392003920039
800242003815000392580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000502004162220035080000102003920039200392003920039
800242003815000392580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000502004162220035080000102003920039200392003920039