Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SHSUB (vector, 2S)

Test 1: uops

Code:

  shsub v0.2s, v0.2s, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000073216111787100020382038203820382038
1004203715008216872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116874910001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715008416872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203716006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203716006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  shsub v0.2s, v0.2s, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000061196872510100100100001001000050028476802001802003720037184223187451010020010000200200002003720037111020110099100100100001000107102162219791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476802001802003720037184223187451010020010000200200002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476802001802003720037184223187451010020010000200200002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476802001802003720037184223187451010020010000200200002003720037111020110099100100100001000007102162219791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476802001802008620037184223187451010020010000200200002003720037111020110099100100100001000107102162219791100001002003820038200382003820038
102042003714900061196872510100100100001001000050028476802001802003720037184223187451010020010000200200002003720037111020110099100100100001000107102162219791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476802001802003720037184223187451010020010000200200002003720037111020110099100100100001000307102162219791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476802001802003720037184223187451010020010000200200002003720037211020110099100100100001000307102162219791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476802001802003720037184223187451010020010000200200002003720037111020110099100100100001000407102162219791100001002003820038200382003820038
1020420037150000611968710110100100100001001000050028476802001802003720037184223187451010020010000200200002003720037111020110099100100100001000007102162219791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371490000000611968725100101010000131000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000100006402162219859010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000400006402172219785010000102003820038200382003820038
100242003714900000006119687251001010100001010000502847680200182008420037184443187671001020100002020000200372003711100211091010100001000006072006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000000006402162219785010000102003820038200382003820038
10024200371500000000611968743100241010000101000060284768020018200372003718444318767100102010000202000020037200371110021109101010000100000100006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000600006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000200006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768020018200372003718444318767100102010000202000020037200371110021109101010000100000000006402162219785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  shsub v0.2s, v1.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0318191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150020066196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000100071011611197910100001002003820038200382003820038
1020420037150400061196762510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000400071011611197910100001002003820038200382003820038
1020420037151000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
1020420037150000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071011611198970100001002003820038200382003820038
1020420037150000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038
1020420037150000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000106071011611197910100001002003820038200382003820038
1020420037150000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000100071011611197910100001002003820038200382003820038
1020420037150000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002008520038200382003820038
1020420037150000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000020071011611197910100001002003820038200382003820038
1020420037150000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010000000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)09181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420225150000089196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000030640416431978510000102003820038200382003820038
1002420037150000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000640416441978510000102003820038200382003820038
100242003715000016861196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001001060640416431978510000102003820038200382003820038
1002420037150000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000640416341978510000102003820038200382003820038
1002420037150000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000640416431978510000102003820038200382003820038
1002420037150000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000640316431978510000102003820038200382003820038
1002420037150000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000640416431978510000102003820038200382003820038
1002420037150000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000200640416341978510000102003820038200382003820038
1002420037150000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000640416431978510000102003820038200382003820038
1002420037150000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000640416341978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  shsub v0.2s, v8.2s, v9.2s
  shsub v1.2s, v8.2s, v9.2s
  shsub v2.2s, v8.2s, v9.2s
  shsub v3.2s, v8.2s, v9.2s
  shsub v4.2s, v8.2s, v9.2s
  shsub v5.2s, v8.2s, v9.2s
  shsub v6.2s, v8.2s, v9.2s
  shsub v7.2s, v8.2s, v9.2s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420048150040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000051105164420035800001002003920039200392003920039
8020420038150040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051104164520035800001002003920039200392003920039
8020420038150040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051105164520035800001002003920039200392003920039
8020420038150040838010010080000100800005006400000200192003820038997339996801002008000020016019420087200381180201100991001008000010000051105165420035800001002003920039200392003920039
8020420038150040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000051105165420035800001002003920039200392003920039
8020420038150040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051105164520035800001002003920039200392003920039
8020420038150040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051104163520035800001002003920039200392003920039
8020420038150040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051105165420035800001002003920039200392003920039
8020420038150040258010010080000100800975006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051105164520035800001002003920039200392003920039
8020420038150040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000051104163520035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)dfe0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200391500456258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000050240416334200357380000102003920039200392003920039
8002420038150039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000350240316325200351580000102003920039200392003920039
800242003815003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100005024341632420035080000102003920039200392003920039
800242003815003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100035024031633420035080000102003920039200392003920039
800242003815003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100005026021632420035080000102003920039200392003920039
800242003815003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100005024331623420035080000102003920039200392003920039
80024200381501596025800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100105024031633420035080000102003920039200392003920039
8002420038150039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000050240316324200351580000102003920039200392003920039
80024200381500134258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000350240316334200352080000102003920039200392003920039
800242003815003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100005024031623420035080000102003920039200392003920039