Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SHSUB (vector, 4H)

Test 1: uops

Code:

  shsub v0.4h, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371606116872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
1004203715031016872510001000100026468002018203720371572318951000100020002037203711100110000373216221787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371606116872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371507916872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073216221787100020382038203820382038

Test 2: Latency 1->2

Code:

  shsub v0.4h, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100001000071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
1020420037150006119687431010010010000108100005002848963020018200372003718422318745101002001000020020328200372003711102011009910010010000100400702071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120126200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500000611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001006405162219785010000102003820038200382003820038
10024200371500000611968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211091010100001006403162219785010000102003820038200382003820038
10024200371500000611968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211091010100001006402162219785010000102003820038200382003820038
10024200371500000611968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211091010100001006403162219785010000102003820038200852003820038
10024200371500009611968725100101010000101000050284768002001802013320037184483187671001020100002020000200372003711100211091010100001006403162219785010000102003820038200382003820038
10024200371500000611968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211091010100001006402162219785010000102003820038200382003820038
10024200371500000611968725100231010000101000050284768002001802003720037184443187671001020100002020000200372003711100211091010100001006402162219785010000102003820038200382003820038
10024200371500000611968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211091010100001006403162219785010000102003820038200382003820038
100242003715000001031968725100101010000101000050284768002001802003720037184443187671001020100002020000200372003711100211091010100001006402162219785010000102003820038200382003820038
10024200371500000611968725100101010000101000050284768002001832003720037184443187671001020100002020000200372003711100211091010100001006403162219785210000102003820038200382003820038

Test 3: Latency 1->3

Code:

  shsub v0.4h, v1.4h, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000000006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
102042003715000000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
102042003715000000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
102042003715000000006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
1020420037150000000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000710116111979121100001002003820038200382003820038
102042003715000000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
102042003715000000006119667251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
1020420037150000000012419687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
102042003715000000008419687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
102042003715000000006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785210000102003820038200382003820038
1002420037150000000042019687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100100006402162219785010000102003820038200382003820038
1002420037150000012006119687251001010100001010000502847680120018200372003718444718767100102010000202000020085200374110021109101010000100000006712162219785010000102003820038200382008620038
100242008415000000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100103006402162219785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100003006402162219785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038
100242003715000000006119687251001010100361010000502851529120018200372003718444318767100102010000202000020037200371110021109101010000100003006402162219785010000102003820038200382003820038
1002420037150000000034519687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000006402162219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  shsub v0.4h, v8.4h, v9.4h
  shsub v1.4h, v8.4h, v9.4h
  shsub v2.4h, v8.4h, v9.4h
  shsub v3.4h, v8.4h, v9.4h
  shsub v4.4h, v8.4h, v9.4h
  shsub v5.4h, v8.4h, v9.4h
  shsub v6.4h, v8.4h, v9.4h
  shsub v7.4h, v8.4h, v9.4h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)181e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042006015000004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051103161220035800001002003920039200392003920039
802042003815000004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
8020420038150001804025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
8020420038150000061518010210980093100800965006400000200192003820038997331002380102200800002001600002003820038118020110099100100800001000051101251120035800001002003920039200392003920039
802042003815000132884025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
802042003815000004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
802042003815000004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820094218020110099100100800001000051101161120035800001002003920039200392003920039
802042003815000004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
802042003815000004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039
802042003814900008225801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420047150003925800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010050203163220035080000102003920039200392003920039
8002420038150003925800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010050203162320035080000102003920039200392003920039
8002420038150003925800101080000108000050640000012001920038200389996310018800102080000201600002003820038118002110910108000010050203163220035080000102003920039200392003920039
800242003815002403925800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010050202162320035080000102003920039200392003920039
8002420038150003925800101080000108000050640000012001920038200389996310018800102080000201600002003820038118002110910108000010050202162320035080000102003920039200392003920039
8002420038150008125800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010050202163320035080000102003920039200392003920039
8002420038150008125800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010050203163220035080000102003920039200392003920039
8002420038150003925800101080000108000050640000002001920038200389996310018800102080195201600002003820038118002110910108000010050203163320035080000102003920039200392003920039
8002420038150003925800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010050202163220035080000102003920039200392003920039
80024200381500012325800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010050203163220035080000102003920039200392003920039