Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SHSUB (vector, 4S)

Test 1: uops

Code:

  shsub v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203715012416872510001000100026468020182037203715723189510001000200020372037111001100004073216221787100020382038203820382038
10042037151510316872510001000100026468020182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
100420371606116872510001000100026468020182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
100420371596116872510001000100026468020182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
100420371606116872510001000100026468020182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
100420371506116872510001000100026468020182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
100420371506116872510001000100026468020182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
100420371608416872510001000100026468020182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
100420371506116872510001000100026468020182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
100420371506116872510001000100026468020182037203715723189510001000200020372037111001100000073216221787100020382038203820382038

Test 2: Latency 1->2

Code:

  shsub v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500000611968725101001001000010010000500284768020018200372003718422031874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768020018200372003718422031874510100200100002002000020037200371110201100991001001000010000037101161119791100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768020018200372003718422031874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200872018120038
10204202751511190611968725101001001000010010000500284768020018200372003718422031874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042003715000006119687251010010210000100100005002847680200182003720037184220318745101002001000020020000200372003711102011009910010010000100021007101161119791100001002003820038200382003820038
10204200371500018264611968725101001001000010010000500284768020018200372003718422031874510100200100002002000020037200851110201100991001001000010000007101161119791100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768020018200372003718422031874510100200100002002000020037200371110201100991001001000010000067101161119791100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768020018200372003718422031874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768020018200372003718422031874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
10204200371500000611968725101001001000010010000500284768020018200372003718422031874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150000000012619687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010000006403162219785010000102003820038200382003820038
1002420037150000000052319687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680020018020037200371844431876710010201000020200002003720037111002110910101000010000306402162219785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
100242003715000000008219687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010000306402162219785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010000306402162219785010000102003820038200382003820038
1002420037150000000053619687251001010100001010000502847680120018020037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
100242003715000000006119687251001010100001010000502847680020065020037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  shsub v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150001911968725101001001000010010000500284768012001802003720037184220318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150002081968725101001001000010010000500284768012001802003720037184220318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001802003720037184220318745101002001000020020000200372003711102011009910010010000100007101161119823100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001802003720037184220318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150002291968725101001001000010010000500284768012001802003720037184220318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001802003720037184220318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768012001802003720084184220318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
1020420037150006941968725101001001000010010000500284768002001802003720037184220318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001802003720037184227318745101002001000020020000200372003711102011009910010010000100107101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001802003720037184220318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500124196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
10024200371500251196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
1002420037150061196872510023101004810100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
10024200371500943196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
10024200371500172196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640316331978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  shsub v0.4s, v8.4s, v9.4s
  shsub v1.4s, v8.4s, v9.4s
  shsub v2.4s, v8.4s, v9.4s
  shsub v3.4s, v8.4s, v9.4s
  shsub v4.4s, v8.4s, v9.4s
  shsub v5.4s, v8.4s, v9.4s
  shsub v6.4s, v8.4s, v9.4s
  shsub v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420059150040258010010080000100800005006400000520019200382003899730399968010020080000200160000200382003811802011009910010080000100005110005162220035800001002003920039200392003920039
80204200381500149258010010080000100800005006400001020019200382003899730399968010020080000200160000200382003811802011009910010080000100105110512162220035800001002003920039200392003920039
8020420038150040258010010080000100800005006400000520019200382003899730399968010020080000200160000200382003811802011009910010080000100005110002162220035800001002003920039200392003920039
80204200381500515258010010080000100800005006400001520019200382003899730399968010020080000200160000200382003811802011009910010080000100005110512162220035800001002003920039200392003920039
8020420038150040258010010080188100800005006400000520019200382003899730399968010020080000200160000200382003811802011009910010080000100205110002163220035800001002003920039200392003920039
8020420038150040258010010080000100800005006400000520019200382003899730399968010020080000200160000200382003811802011009910010080000100005110512162220035800001002003920039200392003920039
8020420038150040258010010080000100800005006400001520019200382003899730399968010020080000200160000200382003811802011009910010080000100005110512162220035800001002003920039200392003920039
80204200381502140258010010080000100800005006400001020019200382003899730399968010020080000200160000200382003811802011009910010080000100005110002162220035800001002003920039200392003920039
8020420038149040258010010080000100800005006400000520019200382003899730399968010020080000200160000200382003811802011009910010080000100005110512162220035800001002003920039200392003920039
80204200381500103258010010080000100800005006400000520019200382003899730399968010020080000200160000200382003811802011009910010080000100005110002162220035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200391500000000832580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000000005020221613920035080000102003920039200392003920039
80024200381500000000392580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000000005020161681220035080000102003920039200392003920039
800242003815000000003142580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000000005020161691320035080000102003920039200392003920039
80024200381500000000392580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000000005020151691220035080000102003920039200392003920039
80024200381500000000392580010108000010800005064000011200192003820038999631001880010208000020160000200382003811800211091010800001000000005020121612820035080000102003920039200392003920039
80024200381490000000392580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000000005020101613820035080000102003920039200392003920039
80024200381500000000392580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000000005020181691220035080000102003920039200392003920039
80024200381500000000392580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000000005020111681220035080000102003920078200392003920039
800242003815000000003925800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010000000050201016131320035080000102003920039200392003920039
80024200381500000000392580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000000005020141691320035080000102003920039200392003920039