Firestorm: SLI (vector, 2D) measurements

Code:

  sli v0.2d, v1.2d, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	2	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	84	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	24	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	2	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	9	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	7	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->1

Code:

  sli v0.2d, v1.2d, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	72	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	19791	1	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	12	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	507	82	19687	25	10100	100	10000	100	10000	500	2848963	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	21	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	465	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	192	441	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	120	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	24	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	149	0	27	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	151	0	3	0	726	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	3	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2852812	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	12	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	12	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038

Test 3: Latency 1->2

Code:

  sli v0.2d, v0.2d, #3

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	0	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	120	1	1	1	717	16	0	0	19800	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	0	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	12	1	1	1	718	16	0	0	19801	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	0	7	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	16	0	0	19801	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	82	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	0	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	16	0	0	19801	2	10000	100	20038	20038	20038	20038	20038
10204	20037	150	24	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	0	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	16	0	0	19801	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	0	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	153	1	1	1	718	16	0	0	19801	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	0	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	16	0	0	19800	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	0	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	15	1	1	1	718	16	0	0	19800	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19686	25	10100	100	10000	100	10000	500	2849693	1	20018	20037	20037	18428	0	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	16	0	0	19801	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	20018	20037	20037	18428	0	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	16	0	0	19801	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	4e	50	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	61	19686	0	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	114	640	3	16	3	3	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	61	19686	20021	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	138	640	3	16	3	3	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	61	19686	20021	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	117	640	3	16	3	3	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	61	19686	20021	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	3	640	3	16	3	3	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	61	19686	0	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	61	19686	0	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	1	6	640	3	16	3	3	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	61	19686	0	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	61	19686	0	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	61	19686	0	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	61	19686	0	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	3	16	3	3	19786	10000	10	20038	20038	20038	20038	20038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sli v0.2d, v8.2d, #3
  movi v1.16b, 0
  sli v1.2d, v8.2d, #3
  movi v2.16b, 0
  sli v2.2d, v8.2d, #3
  movi v3.16b, 0
  sli v3.2d, v8.2d, #3
  movi v4.16b, 0
  sli v4.2d, v8.2d, #3
  movi v5.16b, 0
  sli v5.2d, v8.2d, #3
  movi v6.16b, 0
  sli v6.2d, v8.2d, #3
  movi v7.16b, 0
  sli v7.2d, v8.2d, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	st unit uop (a7)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20091	150	29	25	80116	100	80016	102	80028	500	640196	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	2	8	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	29	25	80116	100	80016	100	80028	500	640196	0	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	3	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	29	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	4	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	29	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	219	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	1	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	29	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	2	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	29	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	5	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	29	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	29	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	1	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	29	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	1	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2507

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	19	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20075	150	0	0	0	44	29	80010	10	80000	10	80000	50	640000	0	1	20031	20052	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	10046	3	1	1	20	25	2	1	1	23	18	20047	20	1	160000	10	20051	20053	20053	20265	20053
160024	20052	150	0	0	0	44	27	80010	10	80000	10	80000	50	640000	1	1	20031	20052	20050	3	21	80010	20	80000	20	160000	20052	20050	1	1	160021	10	9	10	10	160000	10	44	6	10041	3	1	1	18	25	2	1	1	22	18	20047	20	1	160000	10	20053	20051	20051	20260	20051
160024	20050	150	0	1	0	44	27	80010	10	80000	10	80000	50	640000	1	1	20031	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	3	10045	3	1	1	23	25	2	1	1	18	22	20049	21	1	160000	10	20053	20051	20051	20249	20051
160024	20052	150	0	0	0	44	27	80010	10	80000	10	80000	50	640000	1	1	20040	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	6	10046	3	4	1	24	25	2	1	1	18	22	20047	20	1	160000	10	20053	20053	20051	20267	20062
160024	20050	150	0	0	0	50	29	80010	10	80000	10	80000	50	640000	0	1	20031	20050	20050	3	21	80010	20	80000	20	160000	20050	20059	1	1	160021	10	9	10	10	160000	10	0	0	10040	3	1	1	17	25	2	1	1	21	17	20047	20	1	160000	10	20051	20051	20051	20247	20060
160024	20061	150	0	0	0	44	29	80010	10	80000	10	80000	50	640000	0	1	20040	20059	20059	3	21	80010	20	80000	20	160000	20059	20059	1	1	160021	10	9	10	10	160000	10	0	0	10046	6	5	2	20	36	4	2	2	22	18	20056	40	2	160000	10	20060	20060	20060	20261	20051
160024	20050	150	0	0	0	44	29	80010	10	80297	10	80000	50	640000	0	1	20040	20059	20059	3	21	80010	20	80000	20	160000	20059	20059	1	1	160021	10	9	10	10	160000	10	0	6	10046	6	2	2	20	36	4	2	2	20	20	20056	40	2	160000	10	20060	20060	20060	20280	20060
160024	20059	150	0	0	0	715	27	80010	10	80000	10	80000	50	640000	1	1	20031	20050	20050	3	21	80010	20	80000	20	160000	20052	20052	1	1	160021	10	9	10	10	160000	10	6	0	10043	6	2	2	17	34	4	2	2	16	20	20049	40	2	160000	10	20060	20060	20060	20251	20060
160024	20061	151	0	0	0	50	29	80010	10	80000	10	80000	50	640000	0	1	20040	20059	20050	3	21	80010	20	80000	20	160000	20059	20059	1	1	160021	10	9	10	10	160000	10	0	6	10043	6	5	2	21	36	4	2	2	17	18	20058	40	2	160000	10	20060	20060	20060	20266	20060
160024	20061	150	0	0	0	50	29	80010	10	80000	10	80000	50	640000	0	1	20040	20061	20059	3	21	80010	20	80000	20	160000	20061	20059	1	1	160021	10	9	10	10	160000	10	0	0	10044	6	5	2	19	34	4	2	2	21	23	20058	41	2	160000	10	20060	20060	20060	20268	20062

Test 5: throughput

Count: 16

Code:

  sli v0.2d, v16.2d, #3
  sli v1.2d, v16.2d, #3
  sli v2.2d, v16.2d, #3
  sli v3.2d, v16.2d, #3
  sli v4.2d, v16.2d, #3
  sli v5.2d, v16.2d, #3
  sli v6.2d, v16.2d, #3
  sli v7.2d, v16.2d, #3
  sli v8.2d, v16.2d, #3
  sli v9.2d, v16.2d, #3
  sli v10.2d, v16.2d, #3
  sli v11.2d, v16.2d, #3
  sli v12.2d, v16.2d, #3
  sli v13.2d, v16.2d, #3
  sli v14.2d, v16.2d, #3
  sli v15.2d, v16.2d, #3

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40038	300	9	219	25	160108	100	160008	100	160020	500	1280132	1	40019	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	1	0	1	1	1	10118	16	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	71	25	160108	100	160008	100	160020	500	1280132	1	40019	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	25	6	1	1	1	10118	16	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	12	71	25	160108	100	160108	100	160020	500	1280132	1	40019	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40086	1	1	160201	100	99	100	100	160000	100	2	2	0	50	0	1	1	1	10118	16	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	29	25	160108	100	160008	100	160020	500	1280132	1	40019	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	10	3	1	1	1	10118	16	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	29	25	160108	100	160008	100	160020	500	1280132	1	40019	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	8	0	1	1	1	10118	16	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	21	71	25	160108	100	160008	100	160020	500	1280132	1	40019	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10118	16	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	29	25	160108	100	160008	100	160020	500	1280132	1	40019	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	59	0	1	1	1	10118	16	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	29	25	160108	100	160008	100	160020	500	1280132	1	40019	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10118	16	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	299	0	29	25	160108	100	160008	100	160020	500	1280132	1	40019	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	1	0	1	1	1	10118	16	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	299	0	29	25	160108	100	160008	100	160020	500	1280132	1	40019	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	1	0	1	1	1	10118	16	40035	160000	100	40039	40039	40039	40039	40039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40046	300	0	0	45	25	160010	10	160000	10	160000	50	1280000	1	1	40019	40038	40038	19996	0	3	20018	160010	20	160132	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10025	6	2	1	12	16	4	2	2	9	10	40035	40	16	160000	10	40039	40039	40039	40039	40039
160024	40038	299	0	0	45	25	160010	10	160000	10	160000	50	1280000	1	1	40019	40038	40038	19996	0	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10025	6	2	2	9	16	4	2	2	10	7	40035	40	16	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	45	25	160010	10	160000	10	160000	50	1280000	1	0	40019	40038	40038	19996	0	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	1	5	16	2	1	1	5	10	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	299	0	0	51	25	160010	10	160000	10	160000	50	1280000	1	1	40019	40038	40038	19996	0	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	2	0	0	0	0	10025	3	2	1	5	16	2	2	1	10	5	40035	40	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	45	25	160010	10	160000	10	160000	50	1280000	1	1	40019	40038	40038	19996	0	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10025	3	1	2	10	16	4	1	2	10	5	40035	20	16	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	45	25	160010	10	160000	10	160000	50	1280000	0	0	40019	40038	40038	19996	0	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10025	6	2	2	10	16	4	2	2	5	10	40035	40	16	160000	10	40039	40039	40039	40039	40039
160024	40091	300	0	0	51	25	160010	10	160000	10	160000	50	1280000	1	0	40019	40038	40038	19996	0	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10025	3	1	2	5	16	4	1	2	5	10	40035	20	16	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	51	25	160010	10	160000	10	160000	50	1280000	1	1	40019	40038	40038	19996	0	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	1	10	16	2	1	1	6	11	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40090	313	0	0	45	25	160010	10	160000	10	160000	50	1280000	1	1	40019	40038	40038	19996	0	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	9	10022	3	1	1	10	16	2	1	1	5	10	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	299	0	0	710	25	160010	10	160000	10	160000	50	1280000	0	1	40019	40038	40038	19996	0	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	1	5	16	2	1	1	5	10	40035	20	8	160000	10	40039	40039	40039	40039	40039

SLI (vector, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations