Firestorm: SLI (vector, 2S) measurements

Code:

  sli v0.2s, v1.2s, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	15	0	0	0	0	82	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	0	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	9	0	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	0	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	0	0	103	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	0	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	0	0	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	180	0	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	39	0	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	2	147	88	1	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->1

Code:

  sli v0.2s, v1.2s, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	18	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	1	0	24	0	103	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	2	16	1	1	19791	0	10000	100	20181	20038	20038	20038	20038
10204	20037	150	0	0	18	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	0	3	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	6	0	103	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	3	0	0	61	19676	25	10133	100	10000	100	10000	500	2847680	1	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	2	0	0	0	0	710	1	16	1	1	19827	0	10000	100	20038	20038	20038	20038	20038
10205	20037	150	0	0	9	1	61	19687	25	10134	100	10000	108	10000	670	2847680	1	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	768	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	6	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	3	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	0	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	27	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	0	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20054	0	20085	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	0	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	0	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	2	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	0	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	0	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	0	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	3	20085	20085	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	0	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	0	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038

Test 3: Latency 1->2

Code:

  sli v0.2s, v0.2s, #3

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	0	61	19686	25	10100	106	10000	100	10000	500	2847521	0	0	20018	20037	20037	18428	7	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	0	0	0	16	0	0	19801	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	5	20018	20037	20037	18428	7	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	0	0	16	0	0	19801	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	0	20018	20037	20037	18428	7	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	0	0	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	0	20018	20037	20037	18428	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	0	0	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	0	20018	20037	20037	18428	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	0	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	0	20018	20037	20037	18428	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	0	0	0	16	0	0	19801	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	0	20018	20037	20037	18428	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	0	0	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	0	20018	20037	20037	18428	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	0	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	0	20018	20037	20037	18428	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	5	1	0	16	0	0	19801	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	1	5	20018	20037	20037	18428	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	0	0	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	24	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	231	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18788	10010	20	10000	20	20000	20037	20037	1	1	10022	10	9	10	10	10000	10	0	0	0	0	147	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18785	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sli v0.2s, v8.2s, #3
  movi v1.16b, 0
  sli v1.2s, v8.2s, #3
  movi v2.16b, 0
  sli v2.2s, v8.2s, #3
  movi v3.16b, 0
  sli v3.2s, v8.2s, #3
  movi v4.16b, 0
  sli v4.2s, v8.2s, #3
  movi v5.16b, 0
  sli v5.2s, v8.2s, #3
  movi v6.16b, 0
  sli v6.2s, v8.2s, #3
  movi v7.16b, 0
  sli v7.2s, v8.2s, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2509

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20078	151	0	29	25	80116	100	80016	100	80028	500	640196	0	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	29	25	80116	100	80016	100	80028	500	640196	0	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	29	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	3	1	1	1	10119	0	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	29	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	3	1	1	1	10119	0	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	590	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	3	1	1	1	10119	0	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	29	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	0	20129	0	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	29	25	80116	100	80016	100	80028	500	640196	0	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	29	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	30	1	1	1	10119	0	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	29	25	80116	100	80016	100	80028	500	640196	0	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	3	1	1	1	10119	0	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	29	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10119	0	16	0	0	20062	0	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2507

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20075	150	0	0	44	27	80010	10	80000	10	80000	50	640000	1	1	5	20031	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	18	10028	13	4	1	7	25	2	1	1	5	4	20047	271	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	9	44	27	80010	10	80000	10	80000	50	640000	1	1	10	20031	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10026	13	7	1	3	25	2	1	1	3	5	20047	285	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	0	44	27	80010	10	80000	10	80000	50	640000	1	1	10	20031	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10028	13	8	1	5	25	2	1	1	5	3	20047	271	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	0	44	27	80010	10	80000	10	80000	50	640000	1	1	10	20031	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10031	13	8	2	5	25	4	1	2	5	3	20047	276	1	160000	10	20060	20060	20060	20051	20060
160024	20059	150	1	0	44	29	80010	10	80000	10	80000	50	640000	0	1	10	20040	20059	20059	3	21	80010	20	80000	20	160000	20059	20059	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10029	16	9	1	3	34	2	2	2	9	7	20056	286	2	160000	10	20060	20060	20060	20051	20060
160024	20059	150	0	0	50	29	80010	10	80000	10	80000	50	640000	1	1	10	20040	20059	20059	3	21	80010	20	80000	20	160000	20059	20059	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10031	16	8	2	5	25	4	1	2	5	3	20376	262	1	160000	10	20060	20060	20060	20051	20051
160024	20059	150	0	0	44	29	80010	10	80000	10	80000	50	640000	0	1	10	20040	20059	20050	3	21	80010	20	80000	20	160202	20137	20127	2	1	160021	10	9	10	10	160000	10	0	0	0	0	10029	16	9	2	3	67	2	2	2	3	5	20056	277	2	160000	10	20051	20060	20060	20060	20060
160024	20059	153	0	0	50	27	80010	10	80000	10	80000	50	640000	0	1	10	20040	20059	20059	3	21	80010	20	80000	20	160000	20050	20059	1	1	160021	10	9	10	10	160000	10	2	0	0	0	10028	16	8	1	3	34	2	2	2	3	5	20375	268	1	160000	10	20060	20051	20473	20051	20060
160024	20059	150	0	0	50	29	80010	10	80000	10	80000	50	640000	1	1	10	20040	20059	20050	3	21	80010	20	80000	20	160000	20050	20059	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10029	16	9	2	5	34	2	2	1	3	5	20056	268	2	160000	10	20060	20060	20051	20060	20060
160024	20059	150	0	0	50	29	80010	10	80000	10	80000	50	640000	0	1	10	20040	20050	20059	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	2	0	0	10029	16	7	2	5	25	2	2	1	4	5	20047	303	2	160000	10	20060	20060	20051	20060	20060

Test 5: throughput

Count: 16

Code:

  sli v0.2s, v16.2s, #3
  sli v1.2s, v16.2s, #3
  sli v2.2s, v16.2s, #3
  sli v3.2s, v16.2s, #3
  sli v4.2s, v16.2s, #3
  sli v5.2s, v16.2s, #3
  sli v6.2s, v16.2s, #3
  sli v7.2s, v16.2s, #3
  sli v8.2s, v16.2s, #3
  sli v9.2s, v16.2s, #3
  sli v10.2s, v16.2s, #3
  sli v11.2s, v16.2s, #3
  sli v12.2s, v16.2s, #3
  sli v13.2s, v16.2s, #3
  sli v14.2s, v16.2s, #3
  sli v15.2s, v16.2s, #3

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	db	dd	e0	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40059	300	0	0	0	0	29	25	160108	100	160008	100	160020	500	1280132	0	40019	0	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	0	16	0	0	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	29	25	160108	100	160008	100	160020	500	1280132	0	40019	0	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	0	16	0	0	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	71	25	160108	100	160008	100	160020	500	1280132	0	40019	0	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	0	16	0	0	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	299	0	0	0	6	29	25	160108	100	160008	100	160020	500	1280132	0	40019	0	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	0	16	0	0	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	29	25	160108	100	160008	100	160020	500	1280132	0	40019	3	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	0	16	0	0	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	29	25	160108	100	160008	100	160020	500	1280132	0	40019	0	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10137	0	16	0	0	40035	16	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	694	25	160108	100	160008	100	160020	500	1280132	0	40019	0	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	0	16	0	0	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	29	25	160108	100	160008	100	160020	500	1280132	0	40019	0	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	0	16	0	0	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	299	0	0	0	0	29	25	160108	100	160008	100	160020	500	1280132	0	40019	0	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	0	16	0	0	40035	0	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	29	25	160108	100	160008	100	160020	500	1280132	0	40019	0	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	3	1	1	1	10118	0	16	0	0	40035	0	160000	100	40039	40039	40100	40039	40177

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss instruction (0a)	19	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40049	300	0	0	0	0	0	51	25	160010	10	160000	10	160000	50	1280000	1	40019	40038	40038	19989	3	20011	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10024	6	2	2	4	16	4	40	4	3	5	40035	40	15	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	0	51	25	160010	10	160000	10	160000	50	1280000	1	40019	40038	40038	19989	3	20011	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10024	6	2	2	5	16	4	35	4	4	2	40035	40	15	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	0	51	25	160010	10	160000	10	160000	50	1280000	1	40019	40038	40038	19989	3	20011	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10024	6	2	2	2	16	4	30	4	4	4	40035	40	15	160000	10	40113	40111	40220	40039	40039
160024	40038	300	0	0	0	0	0	57	25	160010	10	160000	10	160000	50	1280000	1	40019	40038	40038	19989	3	20011	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10024	6	2	2	2	16	35	37	4	4	4	40035	40	15	160000	10	40039	40039	40039	40039	40039
160024	40038	299	0	0	0	0	0	241	25	160010	10	160000	10	160000	50	1280000	1	40019	40038	40038	19989	3	20011	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10024	6	2	2	2	16	4	38	4	3	3	40035	40	15	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	0	51	25	160010	10	160000	10	160000	50	1280000	1	40019	40038	40038	19989	3	20011	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10024	6	2	2	4	16	4	37	4	4	4	40035	40	15	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	0	51	25	160010	10	160000	10	160000	50	1280000	1	40019	40038	40038	19989	3	20011	160010	20	160000	20	320000	40038	40038	2	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10024	6	2	2	4	16	4	37	4	4	4	40035	60	15	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	0	51	25	160010	10	160000	10	160000	50	1280000	1	40019	40038	40038	19989	3	20011	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10024	6	2	2	3	16	4	41	4	3	4	40035	40	15	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	0	51	25	160010	10	160000	10	160000	50	1280000	1	40019	40038	40038	19989	3	20011	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10024	6	2	2	3	16	4	37	4	4	4	40035	40	15	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	0	51	25	160010	10	160000	10	160000	50	1280000	1	40019	40038	40038	19989	3	20011	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10024	6	2	2	5	16	4	36	4	4	3	40035	40	15	160000	10	40039	40039	40039	40039	40039

SLI (vector, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations