Firestorm: SLI (vector, 4S) measurements

Code:

  sli v0.4s, v1.4s, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	15	3	132	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	147	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	16	0	61	1687	25	1000	1000	1000	264680	1	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->1

Code:

  sli v0.4s, v1.4s, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20083	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	109	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	149	0	15	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	156	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	19791	21	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	710	1	16	1	1	19791	0	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	149	0	0	6	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	1	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19785	10000	10	20038	20038	20038	20038	20038

Test 3: Latency 1->2

Code:

  sli v0.4s, v0.4s, #3

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18428	6	18733	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	722	2	24	2	2	19787	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	747	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18409	6	18733	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	722	2	24	2	2	19787	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	97	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18409	6	18733	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	722	2	24	2	2	19787	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	0	97	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18409	6	18733	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	722	2	24	2	2	19787	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	1	97	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18409	6	18733	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	722	2	24	2	2	19787	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	1	97	19666	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18409	6	18733	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	1	3	0	1	1	1	722	2	24	2	2	19787	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	1	97	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18409	6	18733	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	722	2	24	2	2	19787	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	1	97	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18409	6	18733	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	722	2	24	2	2	19787	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	1	97	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18409	6	18733	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	722	2	24	2	2	19787	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	1	97	19686	25	10100	100	10000	100	10000	500	2847521	0	20018	20037	20037	18409	6	18733	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	1	1	722	2	24	2	2	19787	10000	100	20038	20038	20087	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	45	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20180	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	124	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	6	61	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	3	18767	10010	20	10000	20	20672	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	726	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sli v0.4s, v8.4s, #3
  movi v1.16b, 0
  sli v1.4s, v8.4s, #3
  movi v2.16b, 0
  sli v2.4s, v8.4s, #3
  movi v3.16b, 0
  sli v3.4s, v8.4s, #3
  movi v4.16b, 0
  sli v4.4s, v8.4s, #3
  movi v5.16b, 0
  sli v5.4s, v8.4s, #3
  movi v6.16b, 0
  sli v6.4s, v8.4s, #3
  movi v7.16b, 0
  sli v7.4s, v8.4s, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20090	150	0	29	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	1	1	1	10120	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	29	25	80116	100	80016	100	80028	500	640196	0	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	1	1	1	10120	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	29	25	80116	100	80016	100	80028	500	640196	0	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20157
160204	20065	150	0	29	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	1	1	1	10141	1	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	152	0	29	25	80116	100	80016	100	80028	500	640196	0	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	1	1	1	10120	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	134	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	92	25	80116	100	80016	100	80028	500	640196	1	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	1	1	1	10120	1	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	29	25	80116	100	80016	100	80028	500	640196	0	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	1	1	1	10120	0	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	29	25	80116	100	80016	100	80028	500	640196	0	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	29	25	80116	100	80016	100	80028	500	640196	0	20044	20065	20065	6	12	80224	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	1	1	1	10119	0	16	1	1	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20062	151	0	2	0	0	0	0	0	0	0	0	44	25	80010	10	80000	10	80000	50	640000	1	1	20026	20045	20045	3	21	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10155	6	2	2	1	34	26	3	2	2	29	27	20048	31	0	160000	10	20052	20052	20052	20052	20052
160024	20051	150	1	0	0	1	0	0	0	0	0	1	85	25	80010	10	80000	10	80000	50	640000	0	1	20032	20051	20051	3	21	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10136	6	2	2	1	30	26	3	2	2	24	29	20048	31	0	160000	10	20052	20052	20052	20052	20052
160024	20051	150	1	2	0	3	0	0	0	0	0	0	85	25	80010	10	80000	10	80000	50	640000	0	1	20032	20051	20051	3	21	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10121	6	2	2	1	18	26	3	2	2	30	19	20048	31	0	160000	10	20052	20052	20052	20052	20052
160024	20051	150	1	3	0	3	0	0	0	0	0	1	237	25	80010	10	80000	10	80000	50	640000	0	1	20032	20051	20051	3	21	80010	20	80000	20	160000	20262	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10121	6	2	2	1	29	26	3	2	2	23	31	20048	31	0	160000	10	20052	20052	20052	20052	20052
160024	20051	150	1	2	0	2	0	0	0	0	0	0	100	25	80010	10	80000	10	80000	50	640000	0	1	20032	20051	20051	3	21	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10118	6	2	2	1	29	26	3	2	2	30	30	20048	31	0	160000	10	20052	20052	20052	20052	20052
160024	20051	150	1	3	0	3	0	0	0	0	0	0	85	25	80010	10	80000	10	80000	50	640000	0	1	20032	20051	20051	3	21	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10114	6	2	2	1	26	26	3	2	2	18	30	20048	31	0	160000	10	20052	20052	20052	20052	20052
160024	20051	151	1	3	0	3	0	0	0	0	0	1	97	25	80010	10	80000	10	80000	50	640000	0	1	20032	20051	20051	3	21	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10110	6	2	2	1	30	26	3	2	2	29	29	20048	31	18	160000	10	20052	20052	20052	20052	20052
160024	20051	150	1	2	0	2	0	0	0	0	0	0	91	25	80010	10	80000	10	80000	50	640000	0	1	20032	20051	20051	3	21	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10121	6	2	2	1	30	26	3	2	2	29	29	20048	31	0	160000	10	20052	20052	20052	20052	20052
160024	20051	150	1	2	0	3	0	0	0	0	0	0	465	25	80010	10	80000	10	80000	50	640000	0	1	20032	20051	20051	3	21	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10117	6	2	2	1	18	26	3	2	2	30	21	20048	31	0	160000	10	20052	20052	20052	20052	20052
160024	20051	150	1	3	0	3	0	0	0	0	0	0	85	25	80010	10	80000	10	80000	50	640000	0	1	20032	20051	20051	3	21	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	10120	6	2	2	1	28	26	3	2	2	29	31	20048	31	0	160000	10	20052	20052	20052	20052	20052

Test 5: throughput

Count: 16

Code:

  sli v0.4s, v16.4s, #3
  sli v1.4s, v16.4s, #3
  sli v2.4s, v16.4s, #3
  sli v3.4s, v16.4s, #3
  sli v4.4s, v16.4s, #3
  sli v5.4s, v16.4s, #3
  sli v6.4s, v16.4s, #3
  sli v7.4s, v16.4s, #3
  sli v8.4s, v16.4s, #3
  sli v9.4s, v16.4s, #3
  sli v10.4s, v16.4s, #3
  sli v11.4s, v16.4s, #3
  sli v12.4s, v16.4s, #3
  sli v13.4s, v16.4s, #3
  sli v14.4s, v16.4s, #3
  sli v15.4s, v16.4s, #3

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40059	299	0	0	0	0	0	0	71	25	160108	100	160008	100	160020	500	1280132	1	40019	40038	40038	19977	0	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10118	16	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	0	0	29	25	160108	100	160008	100	160020	500	1280132	0	40019	40038	40038	19977	0	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10118	16	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	0	0	29	25	160108	100	160008	100	160020	500	1280132	0	40019	40038	40038	19977	0	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10118	16	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	0	0	71	25	160108	100	160008	100	160020	500	1280132	1	40019	40038	40088	19977	0	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10118	16	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	299	0	0	0	0	0	0	29	25	160108	100	160008	100	160020	500	1280132	1	40019	40038	40038	19977	0	6	19989	160120	200	160032	200	320064	40240	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10118	16	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	0	0	29	25	160108	100	160008	100	160020	500	1280132	1	40019	40038	40038	19977	0	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10118	16	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	0	0	29	25	160108	100	160008	100	160020	500	1280132	1	40019	40038	40038	19977	0	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10118	16	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	0	0	52	25	160108	100	160008	100	160020	500	1280132	1	40019	40038	40038	19977	0	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10118	16	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	0	0	0	0	0	29	25	160108	100	160008	100	160020	500	1280132	0	40019	40038	40038	19977	0	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10118	16	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	1	0	0	0	0	0	219	25	160108	100	160008	100	160020	500	1280132	0	40019	40038	40038	19977	0	6	19989	160120	200	160427	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	0	1	1	1	10118	16	40035	160000	100	40039	40039	40039	40039	40039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40039	300	0	0	0	0	0	0	45	25	160010	10	160374	10	160000	50	1280000	1	1	5	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	1	3	16	2	1	1	4	4	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	27	0	45	25	160010	10	160000	10	160000	50	1280000	1	0	10	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	1413	0	10022	13	6	1	4	16	2	2	1	4	4	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	27	0	45	25	160010	10	160000	10	160000	50	1280000	1	0	0	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	13	5	1	4	16	2	1	1	4	5	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	36	0	45	25	160010	10	160000	10	160000	50	1280000	1	0	0	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	13	5	1	4	16	2	1	1	4	4	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	36	0	45	25	160010	10	160000	10	160000	50	1280000	1	1	10	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	7	2	4	16	2	1	1	4	4	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	195	0	45	25	160010	10	160000	10	160000	50	1280000	1	1	10	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	3	1	1	5	16	4	1	2	4	4	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	24	0	45	25	160010	10	160000	10	160000	50	1280000	1	0	10	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	13	7	1	4	16	2	1	2	5	5	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	42	0	158	25	160010	10	160000	10	160000	50	1280000	1	1	10	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10024	13	1	1	3	16	2	1	2	3	3	40035	20	16	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	15	0	72	25	160010	10	160000	10	160000	50	1280000	1	1	10	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10022	13	7	1	5	16	2	1	1	3	3	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	1	0	0	0	0	45	25	160010	10	160000	10	160000	50	1280000	1	0	10	40019	40038	40038	19996	3	20018	160122	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	10024	13	7	1	3	35	4	1	1	4	3	40035	20	8	160000	10	40039	40039	40039	40039	40039

SLI (vector, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations