Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SLI (vector, 8B)

Test 1: uops

Code:

  sli v0.8b, v1.8b, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03181e3a3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203715192661687251000100010002646801201820372037157231895100010002000203720371110011000077416441787100020382038203820382038
1004203715002661687251000100010002646801201820372037157231895100010002000203720371110011000077416441787100020382038203820382038
1004203715002661687251000100010002646801201820372037157231895100010002000203720371110011000077416441787100020382038203820382038
10042037150021611687251000100010002646801201820372037157231895100010002000203720371110011000077416441787100020382038203820382038
1004203715062661687251000100010002646801201820372037157231895100010002000203720371110011000077416441787100020382038203820382038
1004203715002661687251000100010002646801201820372037157231895100010002000203720371110011000077416441787100020382038203820382038
1004203715002661687251000100010002646801201820372037157231895100010002000203720371110011000077416441787100020382038203820382038
1004203715002661687251000100010002646801201820372037157231895100010002000203720371110011000077416441787100020382038203820382038
1004203715002661687251000100010002646801201820372037157231895100010002000203720371110011000077416441787100020382038203820382038
1004203715002871687251000100010002646801201820372037157231895100010002000203720371110011000077416441787100020382038203820382038

Test 2: Latency 1->1

Code:

  sli v0.8b, v1.8b, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150000043819687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
1020420132150000021219687251010010010000100100005002847680200182003720037184223187451010020010000200200002017920037111020110099100100100001000000007101161119791100001002003820038200382003820038
102042003715000008419687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
1020420037150000012819687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
1020420037150001206119687251010010010000100100005002847680200182003720084184223187451010020010000200200002003720037111020110099100100100001000001607101161119791100001002003820038200382003820038
10204200371500000110219687251010010010000100100005002847680200182003720037184293187451010020010000200200002003720037111020110099100100100001002000007101161119791100001002003820038200852013220038
1020420037150000012419687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000400007101161119791100001002003820038200382003820038
102042003715000006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
1020420037150000019119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)183f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150001031968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640216121978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010220640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820132
100242003715001611968725100101010000101000050284768002001820037200371844431876710010201033520200002003720037111002110910101000010000640216221978510000102003820038200382003820038
100242003715010611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720085111002110910101000010000640216221978510000102003820038200382003820038
1002420037150001451968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038

Test 3: Latency 1->2

Code:

  sli v0.8b, v0.8b, #3
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)033a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150061196862510100100100001001000050028475212001820037200371842871874010100200100082002001620037200371110201100991001001000010000011171801600198650100001002003820038200382003820038
1020420037150097196862510100100100001001000050028475212001820037200371840961873310100200100002002000020037200371110201100991001001000010000011172222422197870100001002003820038200382003820038
10204200371500268196862510100100100001001000050028475212001820037200371840961873310100200100002002000020037200371110201100991001001000010000011172222422197870100001002008520038200382003820038
10204200371501859196862510100100100001001000050028475212001820037200371840961873310100200100002002000020037200371110201100991001001000010000011172222422197870100001002003820038200382003820038
10204200371501650196862510100100100001001000050028475212001820037200371840961873310100200100002002000020037200371110201100991001001000010000011172222422197870100001002003820038200382003820038
1020420037150061196862510100100100001001000050028475212001820037200371842861874010100200100082002001620037200371110201100991001001000010000011171701600198000100001002003820038200382003820038
1020420037150061196862510100100100001001000050028475212001820037200371842861874110100200100082002001620037200371110201100991001001000010000011171801600198000100001002003820038200382003820038
1020420037150061196862510100100100001001000050028475212001820037200371842861874010100200100082002001620037200371110201100991001001000010010011171701600198010100001002003820038200382003820038
1020420037150061196662510100100100001001000050028475212001820037200371842861874010100200100082002001620037200371110201100991001001000010000011171801600198010100001002003820038200382003820038
1020420037150061196862510100100100001001000050028475212001820037200371842871874010100200100082002001620037200371110201100991001001000010000011171701600198010100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500000006311968625100101010000101000050284752112001820037200371844331876710010201000020200002003720037111002110910101000010000000006403163319786010000102003820038200382003820038
1002420037150000000611968625100101010000101000050284752102001820070200371844331876710010201000020200002003720037111002110910101000010000000006403166319786010000102003820038200382003820038
1002420037150000000611968625100101010000101000050284752112001820037200371844331876710010201000020200002003720037111002110910101000010000000006403163319786010000102003820038200382003820038
1002420037149000000611968625100101010000101000050284752102001820037200371844331876710010201000020200002003720037111002110910101000010000000006403163319786010000102003820038200382003820038
1002420037150000000611968625100101010000101000050284752112001820037200371844331876710010201000020200002003720037111002110910101000010000000106404163319786010000102003820038200382003820038
10024200371500000001911968625100101010000101000050284752112001820037200371844331876710010201000020200002003720037111002110910101000010000000006403163319786010000102003820038200382003820038
1002420037150000000611968625100101010000101000050284752112001820037200371844331876710010201000020200002003720037111002110910101000010000000006403163319786010000102003820038200382003820038
1002420037150000000611968625100101010000101000050284752102001820037200371844331876710010201000020200002003720037111002110910101000010000000006403163319786010000102003820038200382003820038
10024200371500000003651968625100101010000101000050284752112001820037200371844331876710010201000020200002003720037111002110910101000010000000006403163319786010000102003820038200382003820038
1002420037150000000821968625100101010000101000050284752112001820037200371844331876710010201000020200002003720037111002110910101000010000000006403163319786010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sli v0.8b, v8.8b, #3
  movi v1.16b, 0
  sli v1.8b, v8.8b, #3
  movi v2.16b, 0
  sli v2.8b, v8.8b, #3
  movi v3.16b, 0
  sli v3.8b, v8.8b, #3
  movi v4.16b, 0
  sli v4.8b, v8.8b, #3
  movi v5.16b, 0
  sli v5.8b, v8.8b, #3
  movi v6.16b, 0
  sli v6.8b, v8.8b, #3
  movi v7.16b, 0
  sli v7.8b, v8.8b, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss data (0b)18191f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
16020420088151000000029258011610080016100800285006401961200442006520065612801282008002820016005620065200651116020110099100100160000100000011110119116002006201600001002006620066200662006620066
16020420065150000000029258011610080016100800285006401961200442006520065612801282008002820016005620065200651116020110099100100160000100001011110119016002006201600001002006620066200662006620066
160204200651500000000882258011610080016100800285006401961200442006520065612801282008002820016005620065200651116020110099100100160000100000011110119016002006201600001002006620066200662006620066
1602042006515100000001592880119100800191008003150064022012014120076201631010801312008003120016006220076200761116020110099100100160000100000022210130123112007401600001002007720077200782007820077
160204200771510000000642980119100800191008003150064022012005620076200761010801312008003120016006220076200761116020110099100100160000100000022210130123112007401600001002007720077200772007720077
16020420076150000000064298011910080019100800315006402200200562007620076910801312008003120016006220077200761116020110099100100160000100000022210130123112007301600001002007720078200782007720078
16020420077151000000064288011910080019100800315006402200200562007620076910801312008003120016006220076200771116020110099100100160000100000022210130123112007301600001002007720077200782007820078
160204200761500000000499288011910080019100800315006402200200562007620077910801312008003120016006220076200761116020110099100100160000100000022210130123112007301600001002007820077200772007720077
160204200761500000000258298011910080019100800315006402200200562007620077910801312008003120016006220077200761116020110099100100160000100000022210130123112007301600001002007720077200782007720077
160204200761500000000642980119100800191008003150064022012005620076200771010801312008003120016006220076200761116020110099100100160000100010022210130123112007401600001002007720077200772007720078

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaec? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600242006615004425800101080000108000050640000015200262004920045321800102080000201600002004920049111600211091010160000100010030805182422271020046150160000102005020046200502004620046
160024200451500442580010108000010800005064000011520026200452004532180010208000020160000200452004511160021109101016000010001003077519202118620042150160000102005020046200462005020046
160024200451500442580010108000010800005064000011520026200452004532180010208000020160000200452004511160021109101016000010001003277416202117720042150160000102004620046200462004620046
1600242004515004425800101080000108000050640000115200262004520045321800102080000201600002004520045111600211091010160000100010030774110202117720042150160000102004620046200462005020046
160024200491500442580010108000010800005064000001520026200452004532180010208000020160000200492004511160021109101016000010001002974417202117920042150160000102004620046200462004620046
160024200451500502580010108000010800005064000011520026200452004532180010208000020160000200452004511160021109101016000010001003077416202119920042150160000102004620046200462004620046
16002420045150013925800101080000108000050640000111020026200452004532180010208000020160000200452004511160021109101016000010101003382517202117920042150160000102004620046200462004620046
1600242004515004425800101080000108000050640000111020026200452004532180010208000020160000200452004511160021109101016000010001003273517202117520042150160000102004620046200462004620046
16002420045150015125800101080000108000050640000111020026200452004532180010208000020160000200452004511160021109101016000010001003373519202116920042150160000102004620046200462004620046
16002420049150044258001010800001080000506400001110200262004920045321800102080000201600002004520045111600211091010160000100010029736172021171020042150160000102004620046200462004620046

Test 5: throughput

Count: 16

Code:

  sli v0.8b, v16.8b, #3
  sli v1.8b, v16.8b, #3
  sli v2.8b, v16.8b, #3
  sli v3.8b, v16.8b, #3
  sli v4.8b, v16.8b, #3
  sli v5.8b, v16.8b, #3
  sli v6.8b, v16.8b, #3
  sli v7.8b, v16.8b, #3
  sli v8.8b, v16.8b, #3
  sli v9.8b, v16.8b, #3
  sli v10.8b, v16.8b, #3
  sli v11.8b, v16.8b, #3
  sli v12.8b, v16.8b, #3
  sli v13.8b, v16.8b, #3
  sli v14.8b, v16.8b, #3
  sli v15.8b, v16.8b, #3
  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)0318191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
16020440061299006602925160108100160008100160020500128013204001940038400381997661998916012020016003220032006440038400381116020110099100100160000100001111011801600400351600001004003940039400394003940039
1602044003830000300050425160108100160008100160020500128019614002840048400481997691998616012820016003820032007640048400481116020110099100100160000100002221012812311400461600001004004940049400504005040050
16020440049299002706427160116100160016100160028500128019614002840048400481997691998616012820016003820032007640048400491116020110099100100160000100002221012912311400451600001004004940050400494004940049
16020440048299003006427160116100160016100160028500128019614002840048400491997691998616012820016003820032007640048400481116020110099100100160000100002221012812311400461600001004005040050400504005040049
1602044004830000102064271601161001600161001600285001280196140028400484004819976101998616012820016003820032007640049400491116020110099100100160000100002221012812311400451600001004004940050400504005040049
1602044004830001720267261601161001600161001600285001280196140028400484004919976101998616012820016003820032007640049400481116020110099100100160000100002221012812311400451600001004004940049400494004940049
160204400493000048008526160116100160016100160028500128013214001940038400381997761998916012020016003220032006440038400381116020110099100100160000100001111011801600400351600001004003940039400394003940039
160204400383000010802925160108100160008100160020500128013214001940038400381997761998916012020016003220032006440038400381116020110099100100160000100001111011801600400351600001004003940039400394003940039
16020440038299004202925160108100160008100160020500128013214001940038400381997761998916012020016003220032006440038400381116020110099100100160000100001111011801600400351600001004003940039400394003940039
16020440038300002402925160108100160008100160020500128013214001940038400381997761998916012020016003220032006440038400381116020110099100100160000100001111011801600400351600001004003940039400394003940039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03mmu table walk data (08)09181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024400513000002751251600101016000010160000501280000014001940038400381999632001816001020160000203200004003840038111600211091010160000100100223115162113640035208160000104003940039400394003940039
1600244010830000013851251600101016000010160000501280000014001940038400381999632001816001020160000203200004003840038111600211091010160000100100246225164226840035408160000104003940039400394003940039
160024400383000000452516001010160000101600005012800000140019400384003819996320018160010201600002032000040038400381116002110910101600001001002462251642253400354016160000104003940039400394003940039
160024400383000000512516001010160000101600005012800000140019400384003819996320018160010201600002032000040038400381116002110910101600001001002462271642137400354016160000104003940039400394003940039
160024400383000000512516001010160000101600005012800000140019400384003819996320018160010201600002032000040038400381116002110910101600001001002262241642287400354016160000104003940039400394003940039
160024400383000000512516001010160000101600005012800000140019400384003819996320018160010201600002032000040038400381116002110910101600001001002461251622247400352016160000104003940039400394003940039
1600244003830000004315016001010160000101600005012800000140019400384003819996320018160010201600002032000040038400381116002110910101600001001002462251642245400354016160000104003940039400394003940039
1600244003830000060512516001010160000101600005012807240140019400384003819996320018160010201600002032000040038400381116002110910101600001001002462251642255400354016160000104003940039400394003940039
160024400383000000512516001010160000101600005012800000140019400384003819996320018160010201600002032000040038400381116002110910101600001001002462231642235400354016160000104003940039400394003940039
160024400383000000512516001010160000101600005012800000140019400384003819996320018160010201600002032000040038400381116002110910101600001001002462241642245400354016160000104003940039400394003940039