Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
sli v0.8b, v1.8b, #3
movi v0.16b, 1 movi v1.16b, 2
(no loop instructions)
Retires: 1.000
Issues: 1.000
Integer unit issues: 0.000
Load/store unit issues: 0.000
SIMD/FP unit issues: 1.000
retire uop (01) | cycle (02) | 03 | 18 | 1e | 3a | 3f | 4e | 51 | schedule uop (52) | schedule simd uop (54) | dispatch simd uop (57) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map simd uop (7e) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst simd alu (9a) | l1d cache writeback (a8) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? simd retires (ee) | f5 | f6 | f7 | f8 | fd |
1004 | 2037 | 15 | 1 | 9 | 2 | 66 | 1687 | 25 | 1000 | 1000 | 1000 | 264680 | 1 | 2018 | 2037 | 2037 | 1572 | 3 | 1895 | 1000 | 1000 | 2000 | 2037 | 2037 | 1 | 1 | 1001 | 1000 | 0 | 77 | 4 | 16 | 4 | 4 | 1787 | 1000 | 2038 | 2038 | 2038 | 2038 | 2038 |
1004 | 2037 | 15 | 0 | 0 | 2 | 66 | 1687 | 25 | 1000 | 1000 | 1000 | 264680 | 1 | 2018 | 2037 | 2037 | 1572 | 3 | 1895 | 1000 | 1000 | 2000 | 2037 | 2037 | 1 | 1 | 1001 | 1000 | 0 | 77 | 4 | 16 | 4 | 4 | 1787 | 1000 | 2038 | 2038 | 2038 | 2038 | 2038 |
1004 | 2037 | 15 | 0 | 0 | 2 | 66 | 1687 | 25 | 1000 | 1000 | 1000 | 264680 | 1 | 2018 | 2037 | 2037 | 1572 | 3 | 1895 | 1000 | 1000 | 2000 | 2037 | 2037 | 1 | 1 | 1001 | 1000 | 0 | 77 | 4 | 16 | 4 | 4 | 1787 | 1000 | 2038 | 2038 | 2038 | 2038 | 2038 |
1004 | 2037 | 15 | 0 | 0 | 2 | 161 | 1687 | 25 | 1000 | 1000 | 1000 | 264680 | 1 | 2018 | 2037 | 2037 | 1572 | 3 | 1895 | 1000 | 1000 | 2000 | 2037 | 2037 | 1 | 1 | 1001 | 1000 | 0 | 77 | 4 | 16 | 4 | 4 | 1787 | 1000 | 2038 | 2038 | 2038 | 2038 | 2038 |
1004 | 2037 | 15 | 0 | 6 | 2 | 66 | 1687 | 25 | 1000 | 1000 | 1000 | 264680 | 1 | 2018 | 2037 | 2037 | 1572 | 3 | 1895 | 1000 | 1000 | 2000 | 2037 | 2037 | 1 | 1 | 1001 | 1000 | 0 | 77 | 4 | 16 | 4 | 4 | 1787 | 1000 | 2038 | 2038 | 2038 | 2038 | 2038 |
1004 | 2037 | 15 | 0 | 0 | 2 | 66 | 1687 | 25 | 1000 | 1000 | 1000 | 264680 | 1 | 2018 | 2037 | 2037 | 1572 | 3 | 1895 | 1000 | 1000 | 2000 | 2037 | 2037 | 1 | 1 | 1001 | 1000 | 0 | 77 | 4 | 16 | 4 | 4 | 1787 | 1000 | 2038 | 2038 | 2038 | 2038 | 2038 |
1004 | 2037 | 15 | 0 | 0 | 2 | 66 | 1687 | 25 | 1000 | 1000 | 1000 | 264680 | 1 | 2018 | 2037 | 2037 | 1572 | 3 | 1895 | 1000 | 1000 | 2000 | 2037 | 2037 | 1 | 1 | 1001 | 1000 | 0 | 77 | 4 | 16 | 4 | 4 | 1787 | 1000 | 2038 | 2038 | 2038 | 2038 | 2038 |
1004 | 2037 | 15 | 0 | 0 | 2 | 66 | 1687 | 25 | 1000 | 1000 | 1000 | 264680 | 1 | 2018 | 2037 | 2037 | 1572 | 3 | 1895 | 1000 | 1000 | 2000 | 2037 | 2037 | 1 | 1 | 1001 | 1000 | 0 | 77 | 4 | 16 | 4 | 4 | 1787 | 1000 | 2038 | 2038 | 2038 | 2038 | 2038 |
1004 | 2037 | 15 | 0 | 0 | 2 | 66 | 1687 | 25 | 1000 | 1000 | 1000 | 264680 | 1 | 2018 | 2037 | 2037 | 1572 | 3 | 1895 | 1000 | 1000 | 2000 | 2037 | 2037 | 1 | 1 | 1001 | 1000 | 0 | 77 | 4 | 16 | 4 | 4 | 1787 | 1000 | 2038 | 2038 | 2038 | 2038 | 2038 |
1004 | 2037 | 15 | 0 | 0 | 2 | 87 | 1687 | 25 | 1000 | 1000 | 1000 | 264680 | 1 | 2018 | 2037 | 2037 | 1572 | 3 | 1895 | 1000 | 1000 | 2000 | 2037 | 2037 | 1 | 1 | 1001 | 1000 | 0 | 77 | 4 | 16 | 4 | 4 | 1787 | 1000 | 2038 | 2038 | 2038 | 2038 | 2038 |
Code:
sli v0.8b, v1.8b, #3
movi v0.16b, 1 movi v1.16b, 2
(fused SUBS/B.cc loop)
Result (median cycles for code): 2.0037
retire uop (01) | cycle (02) | 03 | l2 tlb miss data (0b) | 19 | 1e | 1f | 3f | 4e | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d tlb access (a0) | l1d tlb miss (a1) | ld unit uop (a6) | l1d cache writeback (a8) | ac | c2 | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
10204 | 20037 | 150 | 0 | 0 | 0 | 0 | 438 | 19687 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847680 | 20018 | 20037 | 20037 | 18422 | 3 | 18745 | 10100 | 200 | 10000 | 200 | 20000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 19791 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
10204 | 20132 | 150 | 0 | 0 | 0 | 0 | 212 | 19687 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847680 | 20018 | 20037 | 20037 | 18422 | 3 | 18745 | 10100 | 200 | 10000 | 200 | 20000 | 20179 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 19791 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
10204 | 20037 | 150 | 0 | 0 | 0 | 0 | 84 | 19687 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847680 | 20018 | 20037 | 20037 | 18422 | 3 | 18745 | 10100 | 200 | 10000 | 200 | 20000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 19791 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
10204 | 20037 | 150 | 0 | 0 | 0 | 0 | 128 | 19687 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847680 | 20018 | 20037 | 20037 | 18422 | 3 | 18745 | 10100 | 200 | 10000 | 200 | 20000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 19791 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
10204 | 20037 | 150 | 0 | 0 | 12 | 0 | 61 | 19687 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847680 | 20018 | 20037 | 20084 | 18422 | 3 | 18745 | 10100 | 200 | 10000 | 200 | 20000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 1 | 6 | 0 | 710 | 1 | 16 | 1 | 1 | 19791 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
10204 | 20037 | 150 | 0 | 0 | 0 | 0 | 1102 | 19687 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847680 | 20018 | 20037 | 20037 | 18429 | 3 | 18745 | 10100 | 200 | 10000 | 200 | 20000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 2 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 19791 | 10000 | 100 | 20038 | 20038 | 20085 | 20132 | 20038 |
10204 | 20037 | 150 | 0 | 0 | 0 | 0 | 124 | 19687 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847680 | 20018 | 20037 | 20037 | 18422 | 3 | 18745 | 10100 | 200 | 10000 | 200 | 20000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 19791 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
10204 | 20037 | 150 | 0 | 0 | 0 | 0 | 61 | 19687 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847680 | 20018 | 20037 | 20037 | 18422 | 3 | 18745 | 10100 | 200 | 10000 | 200 | 20000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 4 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 19791 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
10204 | 20037 | 150 | 0 | 0 | 0 | 0 | 61 | 19687 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847680 | 20018 | 20037 | 20037 | 18422 | 3 | 18745 | 10100 | 200 | 10000 | 200 | 20000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 19791 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
10204 | 20037 | 150 | 0 | 0 | 0 | 0 | 191 | 19687 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847680 | 20018 | 20037 | 20037 | 18422 | 3 | 18745 | 10100 | 200 | 10000 | 200 | 20000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 0 | 0 | 0 | 710 | 1 | 16 | 1 | 1 | 19791 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
Result (median cycles for code): 2.0037
retire uop (01) | cycle (02) | 03 | l2 tlb miss data (0b) | 18 | 3f | 4e | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d cache writeback (a8) | a9 | ac | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
10024 | 20037 | 150 | 0 | 0 | 103 | 19687 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847680 | 0 | 20018 | 20037 | 20037 | 18444 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 20000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 19785 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
10024 | 20037 | 150 | 0 | 0 | 61 | 19687 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847680 | 1 | 20018 | 20037 | 20037 | 18444 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 20000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 2 | 16 | 1 | 2 | 19785 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
10024 | 20037 | 150 | 0 | 0 | 61 | 19687 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847680 | 0 | 20018 | 20037 | 20037 | 18444 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 20000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 2 | 2 | 0 | 640 | 2 | 16 | 2 | 2 | 19785 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
10024 | 20037 | 150 | 0 | 0 | 61 | 19687 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847680 | 0 | 20018 | 20037 | 20037 | 18444 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 20000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 19785 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20132 |
10024 | 20037 | 150 | 0 | 1 | 61 | 19687 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847680 | 0 | 20018 | 20037 | 20037 | 18444 | 3 | 18767 | 10010 | 20 | 10335 | 20 | 20000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 19785 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
10024 | 20037 | 150 | 1 | 0 | 61 | 19687 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847680 | 1 | 20018 | 20037 | 20037 | 18444 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 20000 | 20037 | 20085 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 19785 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
10024 | 20037 | 150 | 0 | 0 | 145 | 19687 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847680 | 0 | 20018 | 20037 | 20037 | 18444 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 20000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 19785 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
10024 | 20037 | 150 | 0 | 0 | 61 | 19687 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847680 | 0 | 20018 | 20037 | 20037 | 18444 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 20000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 19785 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
10024 | 20037 | 150 | 0 | 0 | 61 | 19687 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847680 | 0 | 20018 | 20037 | 20037 | 18444 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 20000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 19785 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
10024 | 20037 | 150 | 0 | 0 | 61 | 19687 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847680 | 0 | 20018 | 20037 | 20037 | 18444 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 20000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 640 | 2 | 16 | 2 | 2 | 19785 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
Code:
sli v0.8b, v0.8b, #3
movi v0.16b, 1
(fused SUBS/B.cc loop)
Result (median cycles for code): 2.0037
retire uop (01) | cycle (02) | 03 | 3a | 3f | 4e | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d cache writeback (a8) | a9 | ac | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
10204 | 20037 | 150 | 0 | 61 | 19686 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847521 | 20018 | 20037 | 20037 | 18428 | 7 | 18740 | 10100 | 200 | 10008 | 200 | 20016 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 1 | 1 | 1 | 718 | 0 | 16 | 0 | 0 | 19865 | 0 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
10204 | 20037 | 150 | 0 | 97 | 19686 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847521 | 20018 | 20037 | 20037 | 18409 | 6 | 18733 | 10100 | 200 | 10000 | 200 | 20000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 1 | 1 | 1 | 722 | 2 | 24 | 2 | 2 | 19787 | 0 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
10204 | 20037 | 150 | 0 | 268 | 19686 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847521 | 20018 | 20037 | 20037 | 18409 | 6 | 18733 | 10100 | 200 | 10000 | 200 | 20000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 1 | 1 | 1 | 722 | 2 | 24 | 2 | 2 | 19787 | 0 | 10000 | 100 | 20085 | 20038 | 20038 | 20038 | 20038 |
10204 | 20037 | 150 | 1 | 859 | 19686 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847521 | 20018 | 20037 | 20037 | 18409 | 6 | 18733 | 10100 | 200 | 10000 | 200 | 20000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 1 | 1 | 1 | 722 | 2 | 24 | 2 | 2 | 19787 | 0 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
10204 | 20037 | 150 | 1 | 650 | 19686 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847521 | 20018 | 20037 | 20037 | 18409 | 6 | 18733 | 10100 | 200 | 10000 | 200 | 20000 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 1 | 1 | 1 | 722 | 2 | 24 | 2 | 2 | 19787 | 0 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
10204 | 20037 | 150 | 0 | 61 | 19686 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847521 | 20018 | 20037 | 20037 | 18428 | 6 | 18740 | 10100 | 200 | 10008 | 200 | 20016 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 1 | 1 | 1 | 717 | 0 | 16 | 0 | 0 | 19800 | 0 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
10204 | 20037 | 150 | 0 | 61 | 19686 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847521 | 20018 | 20037 | 20037 | 18428 | 6 | 18741 | 10100 | 200 | 10008 | 200 | 20016 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 1 | 1 | 1 | 718 | 0 | 16 | 0 | 0 | 19800 | 0 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
10204 | 20037 | 150 | 0 | 61 | 19686 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847521 | 20018 | 20037 | 20037 | 18428 | 6 | 18740 | 10100 | 200 | 10008 | 200 | 20016 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 1 | 0 | 0 | 1 | 1 | 1 | 717 | 0 | 16 | 0 | 0 | 19801 | 0 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
10204 | 20037 | 150 | 0 | 61 | 19666 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847521 | 20018 | 20037 | 20037 | 18428 | 6 | 18740 | 10100 | 200 | 10008 | 200 | 20016 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 1 | 1 | 1 | 718 | 0 | 16 | 0 | 0 | 19801 | 0 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
10204 | 20037 | 150 | 0 | 61 | 19686 | 25 | 10100 | 100 | 10000 | 100 | 10000 | 500 | 2847521 | 20018 | 20037 | 20037 | 18428 | 7 | 18740 | 10100 | 200 | 10008 | 200 | 20016 | 20037 | 20037 | 1 | 1 | 10201 | 100 | 99 | 100 | 100 | 10000 | 100 | 0 | 0 | 0 | 1 | 1 | 1 | 717 | 0 | 16 | 0 | 0 | 19801 | 0 | 10000 | 100 | 20038 | 20038 | 20038 | 20038 | 20038 |
Result (median cycles for code): 2.0037
retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | l2 tlb miss data (0b) | 18 | 19 | 1e | 1f | 3f | 4e | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d tlb access (a0) | ld unit uop (a6) | l1d cache writeback (a8) | a9 | ac | c2 | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
10024 | 20037 | 150 | 0 | 0 | 0 | 0 | 0 | 0 | 631 | 19686 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847521 | 1 | 20018 | 20037 | 20037 | 18443 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 20000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 19786 | 0 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
10024 | 20037 | 150 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 19686 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847521 | 0 | 20018 | 20070 | 20037 | 18443 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 20000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 3 | 16 | 6 | 3 | 19786 | 0 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
10024 | 20037 | 150 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 19686 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847521 | 1 | 20018 | 20037 | 20037 | 18443 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 20000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 19786 | 0 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
10024 | 20037 | 149 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 19686 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847521 | 0 | 20018 | 20037 | 20037 | 18443 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 20000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 19786 | 0 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
10024 | 20037 | 150 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 19686 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847521 | 1 | 20018 | 20037 | 20037 | 18443 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 20000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 640 | 4 | 16 | 3 | 3 | 19786 | 0 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
10024 | 20037 | 150 | 0 | 0 | 0 | 0 | 0 | 0 | 191 | 19686 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847521 | 1 | 20018 | 20037 | 20037 | 18443 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 20000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 19786 | 0 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
10024 | 20037 | 150 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 19686 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847521 | 1 | 20018 | 20037 | 20037 | 18443 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 20000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 19786 | 0 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
10024 | 20037 | 150 | 0 | 0 | 0 | 0 | 0 | 0 | 61 | 19686 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847521 | 0 | 20018 | 20037 | 20037 | 18443 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 20000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 19786 | 0 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
10024 | 20037 | 150 | 0 | 0 | 0 | 0 | 0 | 0 | 365 | 19686 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847521 | 1 | 20018 | 20037 | 20037 | 18443 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 20000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 19786 | 0 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
10024 | 20037 | 150 | 0 | 0 | 0 | 0 | 0 | 0 | 82 | 19686 | 25 | 10010 | 10 | 10000 | 10 | 10000 | 50 | 2847521 | 1 | 20018 | 20037 | 20037 | 18443 | 3 | 18767 | 10010 | 20 | 10000 | 20 | 20000 | 20037 | 20037 | 1 | 1 | 10021 | 10 | 9 | 10 | 10 | 10000 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 640 | 3 | 16 | 3 | 3 | 19786 | 0 | 10000 | 10 | 20038 | 20038 | 20038 | 20038 | 20038 |
Count: 8
Code:
movi v0.16b, 0 sli v0.8b, v8.8b, #3 movi v1.16b, 0 sli v1.8b, v8.8b, #3 movi v2.16b, 0 sli v2.8b, v8.8b, #3 movi v3.16b, 0 sli v3.8b, v8.8b, #3 movi v4.16b, 0 sli v4.8b, v8.8b, #3 movi v5.16b, 0 sli v5.8b, v8.8b, #3 movi v6.16b, 0 sli v6.8b, v8.8b, #3 movi v7.16b, 0 sli v7.8b, v8.8b, #3
movi v8.16b, 9
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.2508
retire uop (01) | cycle (02) | 03 | mmu table walk instruction (07) | mmu table walk data (08) | 09 | l2 tlb miss data (0b) | 18 | 19 | 1f | 3f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d tlb access (a0) | ld unit uop (a6) | a9 | ac | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? int output thing (e9) | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160204 | 20088 | 151 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 29 | 25 | 80116 | 100 | 80016 | 100 | 80028 | 500 | 640196 | 1 | 20044 | 20065 | 20065 | 6 | 12 | 80128 | 200 | 80028 | 200 | 160056 | 20065 | 20065 | 1 | 1 | 160201 | 100 | 99 | 100 | 100 | 160000 | 100 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 10119 | 1 | 16 | 0 | 0 | 20062 | 0 | 160000 | 100 | 20066 | 20066 | 20066 | 20066 | 20066 |
160204 | 20065 | 150 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 29 | 25 | 80116 | 100 | 80016 | 100 | 80028 | 500 | 640196 | 1 | 20044 | 20065 | 20065 | 6 | 12 | 80128 | 200 | 80028 | 200 | 160056 | 20065 | 20065 | 1 | 1 | 160201 | 100 | 99 | 100 | 100 | 160000 | 100 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 10119 | 0 | 16 | 0 | 0 | 20062 | 0 | 160000 | 100 | 20066 | 20066 | 20066 | 20066 | 20066 |
160204 | 20065 | 150 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 882 | 25 | 80116 | 100 | 80016 | 100 | 80028 | 500 | 640196 | 1 | 20044 | 20065 | 20065 | 6 | 12 | 80128 | 200 | 80028 | 200 | 160056 | 20065 | 20065 | 1 | 1 | 160201 | 100 | 99 | 100 | 100 | 160000 | 100 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 10119 | 0 | 16 | 0 | 0 | 20062 | 0 | 160000 | 100 | 20066 | 20066 | 20066 | 20066 | 20066 |
160204 | 20065 | 151 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 159 | 28 | 80119 | 100 | 80019 | 100 | 80031 | 500 | 640220 | 1 | 20141 | 20076 | 20163 | 10 | 10 | 80131 | 200 | 80031 | 200 | 160062 | 20076 | 20076 | 1 | 1 | 160201 | 100 | 99 | 100 | 100 | 160000 | 100 | 0 | 0 | 0 | 0 | 2 | 2 | 2 | 10130 | 1 | 23 | 1 | 1 | 20074 | 0 | 160000 | 100 | 20077 | 20077 | 20078 | 20078 | 20077 |
160204 | 20077 | 151 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 64 | 29 | 80119 | 100 | 80019 | 100 | 80031 | 500 | 640220 | 1 | 20056 | 20076 | 20076 | 10 | 10 | 80131 | 200 | 80031 | 200 | 160062 | 20076 | 20076 | 1 | 1 | 160201 | 100 | 99 | 100 | 100 | 160000 | 100 | 0 | 0 | 0 | 0 | 2 | 2 | 2 | 10130 | 1 | 23 | 1 | 1 | 20074 | 0 | 160000 | 100 | 20077 | 20077 | 20077 | 20077 | 20077 |
160204 | 20076 | 150 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 64 | 29 | 80119 | 100 | 80019 | 100 | 80031 | 500 | 640220 | 0 | 20056 | 20076 | 20076 | 9 | 10 | 80131 | 200 | 80031 | 200 | 160062 | 20077 | 20076 | 1 | 1 | 160201 | 100 | 99 | 100 | 100 | 160000 | 100 | 0 | 0 | 0 | 0 | 2 | 2 | 2 | 10130 | 1 | 23 | 1 | 1 | 20073 | 0 | 160000 | 100 | 20077 | 20078 | 20078 | 20077 | 20078 |
160204 | 20077 | 151 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 64 | 28 | 80119 | 100 | 80019 | 100 | 80031 | 500 | 640220 | 0 | 20056 | 20076 | 20076 | 9 | 10 | 80131 | 200 | 80031 | 200 | 160062 | 20076 | 20077 | 1 | 1 | 160201 | 100 | 99 | 100 | 100 | 160000 | 100 | 0 | 0 | 0 | 0 | 2 | 2 | 2 | 10130 | 1 | 23 | 1 | 1 | 20073 | 0 | 160000 | 100 | 20077 | 20077 | 20078 | 20078 | 20078 |
160204 | 20076 | 150 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 499 | 28 | 80119 | 100 | 80019 | 100 | 80031 | 500 | 640220 | 0 | 20056 | 20076 | 20077 | 9 | 10 | 80131 | 200 | 80031 | 200 | 160062 | 20076 | 20076 | 1 | 1 | 160201 | 100 | 99 | 100 | 100 | 160000 | 100 | 0 | 0 | 0 | 0 | 2 | 2 | 2 | 10130 | 1 | 23 | 1 | 1 | 20073 | 0 | 160000 | 100 | 20078 | 20077 | 20077 | 20077 | 20077 |
160204 | 20076 | 150 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 258 | 29 | 80119 | 100 | 80019 | 100 | 80031 | 500 | 640220 | 0 | 20056 | 20076 | 20077 | 9 | 10 | 80131 | 200 | 80031 | 200 | 160062 | 20077 | 20076 | 1 | 1 | 160201 | 100 | 99 | 100 | 100 | 160000 | 100 | 0 | 0 | 0 | 0 | 2 | 2 | 2 | 10130 | 1 | 23 | 1 | 1 | 20073 | 0 | 160000 | 100 | 20077 | 20077 | 20078 | 20077 | 20077 |
160204 | 20076 | 150 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 64 | 29 | 80119 | 100 | 80019 | 100 | 80031 | 500 | 640220 | 1 | 20056 | 20076 | 20077 | 10 | 10 | 80131 | 200 | 80031 | 200 | 160062 | 20076 | 20076 | 1 | 1 | 160201 | 100 | 99 | 100 | 100 | 160000 | 100 | 0 | 1 | 0 | 0 | 2 | 2 | 2 | 10130 | 1 | 23 | 1 | 1 | 20074 | 0 | 160000 | 100 | 20077 | 20077 | 20077 | 20077 | 20078 |
Result (median cycles for code divided by count): 0.2506
retire uop (01) | cycle (02) | 03 | 1e | 3f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 5f | 60 | 61 | 69 | 6d | 6e | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d cache writeback (a8) | ac | cf | d0 | d2 | l1i cache miss demand (d3) | d5 | map dispatch bubble (d6) | d9 | da | db | dd | fetch restart (de) | e0 | ea | ec | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160024 | 20066 | 150 | 0 | 44 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 0 | 1 | 5 | 20026 | 20049 | 20045 | 3 | 21 | 80010 | 20 | 80000 | 20 | 160000 | 20049 | 20049 | 1 | 1 | 160021 | 10 | 9 | 10 | 10 | 160000 | 10 | 0 | 0 | 10030 | 80 | 5 | 1 | 8 | 24 | 2 | 2 | 2 | 7 | 10 | 20046 | 15 | 0 | 160000 | 10 | 20050 | 20046 | 20050 | 20046 | 20046 |
160024 | 20045 | 150 | 0 | 44 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 1 | 1 | 5 | 20026 | 20045 | 20045 | 3 | 21 | 80010 | 20 | 80000 | 20 | 160000 | 20045 | 20045 | 1 | 1 | 160021 | 10 | 9 | 10 | 10 | 160000 | 10 | 0 | 0 | 10030 | 77 | 5 | 1 | 9 | 20 | 2 | 1 | 1 | 8 | 6 | 20042 | 15 | 0 | 160000 | 10 | 20050 | 20046 | 20046 | 20050 | 20046 |
160024 | 20045 | 150 | 0 | 44 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 1 | 1 | 5 | 20026 | 20045 | 20045 | 3 | 21 | 80010 | 20 | 80000 | 20 | 160000 | 20045 | 20045 | 1 | 1 | 160021 | 10 | 9 | 10 | 10 | 160000 | 10 | 0 | 0 | 10032 | 77 | 4 | 1 | 6 | 20 | 2 | 1 | 1 | 7 | 7 | 20042 | 15 | 0 | 160000 | 10 | 20046 | 20046 | 20046 | 20046 | 20046 |
160024 | 20045 | 150 | 0 | 44 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 1 | 1 | 5 | 20026 | 20045 | 20045 | 3 | 21 | 80010 | 20 | 80000 | 20 | 160000 | 20045 | 20045 | 1 | 1 | 160021 | 10 | 9 | 10 | 10 | 160000 | 10 | 0 | 0 | 10030 | 77 | 4 | 1 | 10 | 20 | 2 | 1 | 1 | 7 | 7 | 20042 | 15 | 0 | 160000 | 10 | 20046 | 20046 | 20046 | 20050 | 20046 |
160024 | 20049 | 150 | 0 | 44 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 0 | 1 | 5 | 20026 | 20045 | 20045 | 3 | 21 | 80010 | 20 | 80000 | 20 | 160000 | 20049 | 20045 | 1 | 1 | 160021 | 10 | 9 | 10 | 10 | 160000 | 10 | 0 | 0 | 10029 | 74 | 4 | 1 | 7 | 20 | 2 | 1 | 1 | 7 | 9 | 20042 | 15 | 0 | 160000 | 10 | 20046 | 20046 | 20046 | 20046 | 20046 |
160024 | 20045 | 150 | 0 | 50 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 1 | 1 | 5 | 20026 | 20045 | 20045 | 3 | 21 | 80010 | 20 | 80000 | 20 | 160000 | 20045 | 20045 | 1 | 1 | 160021 | 10 | 9 | 10 | 10 | 160000 | 10 | 0 | 0 | 10030 | 77 | 4 | 1 | 6 | 20 | 2 | 1 | 1 | 9 | 9 | 20042 | 15 | 0 | 160000 | 10 | 20046 | 20046 | 20046 | 20046 | 20046 |
160024 | 20045 | 150 | 0 | 139 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 1 | 1 | 10 | 20026 | 20045 | 20045 | 3 | 21 | 80010 | 20 | 80000 | 20 | 160000 | 20045 | 20045 | 1 | 1 | 160021 | 10 | 9 | 10 | 10 | 160000 | 10 | 1 | 0 | 10033 | 82 | 5 | 1 | 7 | 20 | 2 | 1 | 1 | 7 | 9 | 20042 | 15 | 0 | 160000 | 10 | 20046 | 20046 | 20046 | 20046 | 20046 |
160024 | 20045 | 150 | 0 | 44 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 1 | 1 | 10 | 20026 | 20045 | 20045 | 3 | 21 | 80010 | 20 | 80000 | 20 | 160000 | 20045 | 20045 | 1 | 1 | 160021 | 10 | 9 | 10 | 10 | 160000 | 10 | 0 | 0 | 10032 | 73 | 5 | 1 | 7 | 20 | 2 | 1 | 1 | 7 | 5 | 20042 | 15 | 0 | 160000 | 10 | 20046 | 20046 | 20046 | 20046 | 20046 |
160024 | 20045 | 150 | 0 | 151 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 1 | 1 | 10 | 20026 | 20045 | 20045 | 3 | 21 | 80010 | 20 | 80000 | 20 | 160000 | 20045 | 20045 | 1 | 1 | 160021 | 10 | 9 | 10 | 10 | 160000 | 10 | 0 | 0 | 10033 | 73 | 5 | 1 | 9 | 20 | 2 | 1 | 1 | 6 | 9 | 20042 | 15 | 0 | 160000 | 10 | 20046 | 20046 | 20046 | 20046 | 20046 |
160024 | 20049 | 150 | 0 | 44 | 25 | 80010 | 10 | 80000 | 10 | 80000 | 50 | 640000 | 1 | 1 | 10 | 20026 | 20049 | 20045 | 3 | 21 | 80010 | 20 | 80000 | 20 | 160000 | 20045 | 20045 | 1 | 1 | 160021 | 10 | 9 | 10 | 10 | 160000 | 10 | 0 | 0 | 10029 | 73 | 6 | 1 | 7 | 20 | 2 | 1 | 1 | 7 | 10 | 20042 | 15 | 0 | 160000 | 10 | 20046 | 20046 | 20046 | 20046 | 20046 |
Count: 16
Code:
sli v0.8b, v16.8b, #3 sli v1.8b, v16.8b, #3 sli v2.8b, v16.8b, #3 sli v3.8b, v16.8b, #3 sli v4.8b, v16.8b, #3 sli v5.8b, v16.8b, #3 sli v6.8b, v16.8b, #3 sli v7.8b, v16.8b, #3 sli v8.8b, v16.8b, #3 sli v9.8b, v16.8b, #3 sli v10.8b, v16.8b, #3 sli v11.8b, v16.8b, #3 sli v12.8b, v16.8b, #3 sli v13.8b, v16.8b, #3 sli v14.8b, v16.8b, #3 sli v15.8b, v16.8b, #3
movi v16.16b, 17
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.2502
retire uop (01) | cycle (02) | 03 | 18 | 19 | 1e | 1f | 3f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | l1d tlb access (a0) | ld unit uop (a6) | branch cond mispred nonspec (c5) | branch mispred nonspec (cb) | cd | cf | d5 | map dispatch bubble (d6) | dd | fetch restart (de) | e0 | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160204 | 40061 | 299 | 0 | 0 | 66 | 0 | 29 | 25 | 160108 | 100 | 160008 | 100 | 160020 | 500 | 1280132 | 0 | 40019 | 40038 | 40038 | 19976 | 6 | 19989 | 160120 | 200 | 160032 | 200 | 320064 | 40038 | 40038 | 1 | 1 | 160201 | 100 | 99 | 100 | 100 | 160000 | 100 | 0 | 0 | 1 | 1 | 1 | 10118 | 0 | 16 | 0 | 0 | 40035 | 160000 | 100 | 40039 | 40039 | 40039 | 40039 | 40039 |
160204 | 40038 | 300 | 0 | 0 | 300 | 0 | 504 | 25 | 160108 | 100 | 160008 | 100 | 160020 | 500 | 1280196 | 1 | 40028 | 40048 | 40048 | 19976 | 9 | 19986 | 160128 | 200 | 160038 | 200 | 320076 | 40048 | 40048 | 1 | 1 | 160201 | 100 | 99 | 100 | 100 | 160000 | 100 | 0 | 0 | 2 | 2 | 2 | 10128 | 1 | 23 | 1 | 1 | 40046 | 160000 | 100 | 40049 | 40049 | 40050 | 40050 | 40050 |
160204 | 40049 | 299 | 0 | 0 | 27 | 0 | 64 | 27 | 160116 | 100 | 160016 | 100 | 160028 | 500 | 1280196 | 1 | 40028 | 40048 | 40048 | 19976 | 9 | 19986 | 160128 | 200 | 160038 | 200 | 320076 | 40048 | 40049 | 1 | 1 | 160201 | 100 | 99 | 100 | 100 | 160000 | 100 | 0 | 0 | 2 | 2 | 2 | 10129 | 1 | 23 | 1 | 1 | 40045 | 160000 | 100 | 40049 | 40050 | 40049 | 40049 | 40049 |
160204 | 40048 | 299 | 0 | 0 | 30 | 0 | 64 | 27 | 160116 | 100 | 160016 | 100 | 160028 | 500 | 1280196 | 1 | 40028 | 40048 | 40049 | 19976 | 9 | 19986 | 160128 | 200 | 160038 | 200 | 320076 | 40048 | 40048 | 1 | 1 | 160201 | 100 | 99 | 100 | 100 | 160000 | 100 | 0 | 0 | 2 | 2 | 2 | 10128 | 1 | 23 | 1 | 1 | 40046 | 160000 | 100 | 40050 | 40050 | 40050 | 40050 | 40049 |
160204 | 40048 | 300 | 0 | 0 | 102 | 0 | 64 | 27 | 160116 | 100 | 160016 | 100 | 160028 | 500 | 1280196 | 1 | 40028 | 40048 | 40048 | 19976 | 10 | 19986 | 160128 | 200 | 160038 | 200 | 320076 | 40049 | 40049 | 1 | 1 | 160201 | 100 | 99 | 100 | 100 | 160000 | 100 | 0 | 0 | 2 | 2 | 2 | 10128 | 1 | 23 | 1 | 1 | 40045 | 160000 | 100 | 40049 | 40050 | 40050 | 40050 | 40049 |
160204 | 40048 | 300 | 0 | 1 | 72 | 0 | 267 | 26 | 160116 | 100 | 160016 | 100 | 160028 | 500 | 1280196 | 1 | 40028 | 40048 | 40049 | 19976 | 10 | 19986 | 160128 | 200 | 160038 | 200 | 320076 | 40049 | 40048 | 1 | 1 | 160201 | 100 | 99 | 100 | 100 | 160000 | 100 | 0 | 0 | 2 | 2 | 2 | 10128 | 1 | 23 | 1 | 1 | 40045 | 160000 | 100 | 40049 | 40049 | 40049 | 40049 | 40049 |
160204 | 40049 | 300 | 0 | 0 | 480 | 0 | 85 | 26 | 160116 | 100 | 160016 | 100 | 160028 | 500 | 1280132 | 1 | 40019 | 40038 | 40038 | 19977 | 6 | 19989 | 160120 | 200 | 160032 | 200 | 320064 | 40038 | 40038 | 1 | 1 | 160201 | 100 | 99 | 100 | 100 | 160000 | 100 | 0 | 0 | 1 | 1 | 1 | 10118 | 0 | 16 | 0 | 0 | 40035 | 160000 | 100 | 40039 | 40039 | 40039 | 40039 | 40039 |
160204 | 40038 | 300 | 0 | 0 | 108 | 0 | 29 | 25 | 160108 | 100 | 160008 | 100 | 160020 | 500 | 1280132 | 1 | 40019 | 40038 | 40038 | 19977 | 6 | 19989 | 160120 | 200 | 160032 | 200 | 320064 | 40038 | 40038 | 1 | 1 | 160201 | 100 | 99 | 100 | 100 | 160000 | 100 | 0 | 0 | 1 | 1 | 1 | 10118 | 0 | 16 | 0 | 0 | 40035 | 160000 | 100 | 40039 | 40039 | 40039 | 40039 | 40039 |
160204 | 40038 | 299 | 0 | 0 | 42 | 0 | 29 | 25 | 160108 | 100 | 160008 | 100 | 160020 | 500 | 1280132 | 1 | 40019 | 40038 | 40038 | 19977 | 6 | 19989 | 160120 | 200 | 160032 | 200 | 320064 | 40038 | 40038 | 1 | 1 | 160201 | 100 | 99 | 100 | 100 | 160000 | 100 | 0 | 0 | 1 | 1 | 1 | 10118 | 0 | 16 | 0 | 0 | 40035 | 160000 | 100 | 40039 | 40039 | 40039 | 40039 | 40039 |
160204 | 40038 | 300 | 0 | 0 | 24 | 0 | 29 | 25 | 160108 | 100 | 160008 | 100 | 160020 | 500 | 1280132 | 1 | 40019 | 40038 | 40038 | 19977 | 6 | 19989 | 160120 | 200 | 160032 | 200 | 320064 | 40038 | 40038 | 1 | 1 | 160201 | 100 | 99 | 100 | 100 | 160000 | 100 | 0 | 0 | 1 | 1 | 1 | 10118 | 0 | 16 | 0 | 0 | 40035 | 160000 | 100 | 40039 | 40039 | 40039 | 40039 | 40039 |
Result (median cycles for code divided by count): 0.2502
retire uop (01) | cycle (02) | 03 | mmu table walk data (08) | 09 | 18 | 1e | 3f | 51 | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | dispatch int uop (56) | dispatch simd uop (57) | int uops in schedulers (59) | ldst uops in schedulers (5b) | 5f | 60 | 69 | 6d | 6e | map stall dispatch (70) | map rewind (75) | map stall (76) | dispatch uop (78) | map int uop (7c) | map simd uop (7e) | map int uop inputs (7f) | map simd uop inputs (81) | 82 | 83 | flush restart other nonspec (84) | 85 | inst all (8c) | inst branch (8d) | inst branch taken (90) | inst branch cond (94) | inst int alu (97) | inst simd alu (9a) | 9f | ac | cf | d0 | d2 | l1i cache miss demand (d3) | d5 | map dispatch bubble (d6) | d9 | da | db | dd | fetch restart (de) | e0 | ea | eb | ? simd retires (ee) | ? int retires (ef) | f5 | f6 | f7 | f8 | fd |
160024 | 40051 | 300 | 0 | 0 | 0 | 27 | 51 | 25 | 160010 | 10 | 160000 | 10 | 160000 | 50 | 1280000 | 0 | 1 | 40019 | 40038 | 40038 | 19996 | 3 | 20018 | 160010 | 20 | 160000 | 20 | 320000 | 40038 | 40038 | 1 | 1 | 160021 | 10 | 9 | 10 | 10 | 160000 | 10 | 0 | 10022 | 3 | 1 | 1 | 5 | 16 | 2 | 1 | 1 | 3 | 6 | 40035 | 20 | 8 | 160000 | 10 | 40039 | 40039 | 40039 | 40039 | 40039 |
160024 | 40108 | 300 | 0 | 0 | 0 | 138 | 51 | 25 | 160010 | 10 | 160000 | 10 | 160000 | 50 | 1280000 | 0 | 1 | 40019 | 40038 | 40038 | 19996 | 3 | 20018 | 160010 | 20 | 160000 | 20 | 320000 | 40038 | 40038 | 1 | 1 | 160021 | 10 | 9 | 10 | 10 | 160000 | 10 | 0 | 10024 | 6 | 2 | 2 | 5 | 16 | 4 | 2 | 2 | 6 | 8 | 40035 | 40 | 8 | 160000 | 10 | 40039 | 40039 | 40039 | 40039 | 40039 |
160024 | 40038 | 300 | 0 | 0 | 0 | 0 | 45 | 25 | 160010 | 10 | 160000 | 10 | 160000 | 50 | 1280000 | 0 | 1 | 40019 | 40038 | 40038 | 19996 | 3 | 20018 | 160010 | 20 | 160000 | 20 | 320000 | 40038 | 40038 | 1 | 1 | 160021 | 10 | 9 | 10 | 10 | 160000 | 10 | 0 | 10024 | 6 | 2 | 2 | 5 | 16 | 4 | 2 | 2 | 5 | 3 | 40035 | 40 | 16 | 160000 | 10 | 40039 | 40039 | 40039 | 40039 | 40039 |
160024 | 40038 | 300 | 0 | 0 | 0 | 0 | 51 | 25 | 160010 | 10 | 160000 | 10 | 160000 | 50 | 1280000 | 0 | 1 | 40019 | 40038 | 40038 | 19996 | 3 | 20018 | 160010 | 20 | 160000 | 20 | 320000 | 40038 | 40038 | 1 | 1 | 160021 | 10 | 9 | 10 | 10 | 160000 | 10 | 0 | 10024 | 6 | 2 | 2 | 7 | 16 | 4 | 2 | 1 | 3 | 7 | 40035 | 40 | 16 | 160000 | 10 | 40039 | 40039 | 40039 | 40039 | 40039 |
160024 | 40038 | 300 | 0 | 0 | 0 | 0 | 51 | 25 | 160010 | 10 | 160000 | 10 | 160000 | 50 | 1280000 | 0 | 1 | 40019 | 40038 | 40038 | 19996 | 3 | 20018 | 160010 | 20 | 160000 | 20 | 320000 | 40038 | 40038 | 1 | 1 | 160021 | 10 | 9 | 10 | 10 | 160000 | 10 | 0 | 10022 | 6 | 2 | 2 | 4 | 16 | 4 | 2 | 2 | 8 | 7 | 40035 | 40 | 16 | 160000 | 10 | 40039 | 40039 | 40039 | 40039 | 40039 |
160024 | 40038 | 300 | 0 | 0 | 0 | 0 | 51 | 25 | 160010 | 10 | 160000 | 10 | 160000 | 50 | 1280000 | 0 | 1 | 40019 | 40038 | 40038 | 19996 | 3 | 20018 | 160010 | 20 | 160000 | 20 | 320000 | 40038 | 40038 | 1 | 1 | 160021 | 10 | 9 | 10 | 10 | 160000 | 10 | 0 | 10024 | 6 | 1 | 2 | 5 | 16 | 2 | 2 | 2 | 4 | 7 | 40035 | 20 | 16 | 160000 | 10 | 40039 | 40039 | 40039 | 40039 | 40039 |
160024 | 40038 | 300 | 0 | 0 | 0 | 0 | 431 | 50 | 160010 | 10 | 160000 | 10 | 160000 | 50 | 1280000 | 0 | 1 | 40019 | 40038 | 40038 | 19996 | 3 | 20018 | 160010 | 20 | 160000 | 20 | 320000 | 40038 | 40038 | 1 | 1 | 160021 | 10 | 9 | 10 | 10 | 160000 | 10 | 0 | 10024 | 6 | 2 | 2 | 5 | 16 | 4 | 2 | 2 | 4 | 5 | 40035 | 40 | 16 | 160000 | 10 | 40039 | 40039 | 40039 | 40039 | 40039 |
160024 | 40038 | 300 | 0 | 0 | 0 | 60 | 51 | 25 | 160010 | 10 | 160000 | 10 | 160000 | 50 | 1280724 | 0 | 1 | 40019 | 40038 | 40038 | 19996 | 3 | 20018 | 160010 | 20 | 160000 | 20 | 320000 | 40038 | 40038 | 1 | 1 | 160021 | 10 | 9 | 10 | 10 | 160000 | 10 | 0 | 10024 | 6 | 2 | 2 | 5 | 16 | 4 | 2 | 2 | 5 | 5 | 40035 | 40 | 16 | 160000 | 10 | 40039 | 40039 | 40039 | 40039 | 40039 |
160024 | 40038 | 300 | 0 | 0 | 0 | 0 | 51 | 25 | 160010 | 10 | 160000 | 10 | 160000 | 50 | 1280000 | 0 | 1 | 40019 | 40038 | 40038 | 19996 | 3 | 20018 | 160010 | 20 | 160000 | 20 | 320000 | 40038 | 40038 | 1 | 1 | 160021 | 10 | 9 | 10 | 10 | 160000 | 10 | 0 | 10024 | 6 | 2 | 2 | 3 | 16 | 4 | 2 | 2 | 3 | 5 | 40035 | 40 | 16 | 160000 | 10 | 40039 | 40039 | 40039 | 40039 | 40039 |
160024 | 40038 | 300 | 0 | 0 | 0 | 0 | 51 | 25 | 160010 | 10 | 160000 | 10 | 160000 | 50 | 1280000 | 0 | 1 | 40019 | 40038 | 40038 | 19996 | 3 | 20018 | 160010 | 20 | 160000 | 20 | 320000 | 40038 | 40038 | 1 | 1 | 160021 | 10 | 9 | 10 | 10 | 160000 | 10 | 0 | 10024 | 6 | 2 | 2 | 4 | 16 | 4 | 2 | 2 | 4 | 5 | 40035 | 40 | 16 | 160000 | 10 | 40039 | 40039 | 40039 | 40039 | 40039 |