Firestorm: SLI (vector, 8H) measurements

Code:

  sli v0.8h, v1.8h, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	2037	15	15	82	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	103	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038
1004	2037	15	0	61	1687	25	1000	1000	1000	264680	0	2018	2037	2037	1572	3	1895	1000	1000	2000	2037	2037	1	1	1001	1000	0	0	73	1	16	1	1	1787	1000	2038	2038	2038	2038	2038

Test 2: Latency 1->1

Code:

  sli v0.8h, v1.8h, #3

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	0	0	357	61	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	9	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	781	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	149	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2848963	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	82	19687	25	10100	100	10000	100	10000	500	2847680	1	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	757	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	61	19687	25	10100	100	10000	100	10152	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	168	61	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	0	82	19687	25	10100	100	10000	100	10000	500	2847680	0	20018	20037	20037	18422	3	18745	10100	200	10000	200	20000	20037	20037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	19791	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	0	0	0	54	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	54	0	61	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20084	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	170	19687	25	10010	10	10000	10	10000	50	2847680	0	20018	20037	20037	18444	3	18767	10010	20	10000	20	20334	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	288	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	3	661	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	1	1	2	219	88	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	3	2	19785	0	10000	10	20038	20038	20038	20038	20074
10024	20037	150	0	0	0	258	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	251	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	0	0	0	0	61	19687	25	10010	10	10000	10	10000	50	2847680	1	20018	20037	20037	18444	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	0	640	2	16	2	2	19785	0	10000	10	20038	20038	20038	20038	20038

Test 3: Latency 1->2

Code:

  sli v0.8h, v0.8h, #3

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	20037	150	255	0	61	19686	25	10115	100	10000	100	10000	500	2847521	20018	20037	20037	18428	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	1	1	1	718	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18428	7	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	1	1	1	718	0	16	0	0	19801	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18428	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	1	1	1	718	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19686	43	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18428	6	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	1	1	1	718	0	16	0	0	19801	10000	100	20038	20038	20038	20038	20038
10204	20037	150	0	0	61	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18441	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	1	1	1	717	0	16	0	0	19801	10000	100	20038	20038	20038	20038	20038
10204	20037	150	18	0	61	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18428	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	1	1	1	718	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	150	6	0	61	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18428	7	18741	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	1	1	1	717	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	150	33	0	61	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18428	7	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	1	1	1	718	0	16	0	0	19800	10000	100	20038	20038	20038	20038	20038
10204	20037	150	51	0	61	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18428	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	1	1	1	717	0	16	0	0	19801	10000	100	20038	20038	20038	20038	20086
10204	20037	150	12	0	61	19686	25	10100	100	10000	100	10000	500	2847521	20018	20037	20037	18428	6	18740	10100	200	10008	200	20016	20037	20037	1	1	10201	100	99	100	100	10000	100	1	1	1	717	0	16	0	0	19801	10000	100	20038	20038	20038	20038	20038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	20037	150	42	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	60	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	12	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	54	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	81	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	661	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20054	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	60	61	19686	25	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	9	61	19686	25	10010	10	10000	10	10000	50	2847521	0	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	33	61	19686	25	10022	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038
10024	20037	150	0	61	19686	44	10010	10	10000	10	10000	50	2847521	1	20018	20037	20037	18443	3	18767	10010	20	10000	20	20000	20037	20037	1	1	10021	10	9	10	10	10000	10	0	640	2	16	2	2	19786	10000	10	20038	20038	20038	20038	20038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  sli v0.8h, v8.8h, #3
  movi v1.16b, 0
  sli v1.8h, v8.8h, #3
  movi v2.16b, 0
  sli v2.8h, v8.8h, #3
  movi v3.16b, 0
  sli v3.8h, v8.8h, #3
  movi v4.16b, 0
  sli v4.8h, v8.8h, #3
  movi v5.16b, 0
  sli v5.8h, v8.8h, #3
  movi v6.16b, 0
  sli v6.8h, v8.8h, #3
  movi v7.16b, 0
  sli v7.8h, v8.8h, #3

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20089	150	0	0	0	21	0	29	25	80116	100	80016	100	80028	500	640196	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	57	0	29	84	80116	100	80016	100	80028	500	640196	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	9	0	29	25	80116	100	80016	100	80028	500	640196	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	15	0	29	25	80116	100	80016	100	80028	500	640196	20044	20065	20065	6	12	80240	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	9	0	29	25	80116	100	80016	100	80028	500	640196	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	0	15	0	29	25	80116	100	80016	100	80028	500	640196	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	81	0	29	25	80116	100	80016	100	80028	500	640196	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	480	2	1	1	1	10119	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	24	0	115	25	80116	100	80016	100	80028	500	640196	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	6	0	242	25	80116	100	80117	100	80028	500	641004	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	3	0	1	1	1	10119	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066
160204	20147	150	0	0	0	384	192	29	25	80116	100	80016	100	80028	500	640196	20044	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	1	0	0	0	1	1	1	10119	1	16	1	1	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20073	150	0	0	0	33	0	44	27	80010	10	80000	10	80000	50	640000	1	1	5	20031	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10031	8	2	1	11	25	2	1	1	10	22	20047	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	0	0	18	0	44	29	80010	10	80000	10	80000	50	640000	1	1	5	20031	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10045	8	2	1	22	25	4	2	2	8	22	20056	20	1	160000	10	20060	20060	20060	20060	20060
160024	20050	150	0	0	0	9	0	44	27	80010	10	80000	10	80000	50	640000	1	1	5	20031	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10032	8	5	2	9	25	2	1	1	22	22	20047	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	0	0	0	0	234	27	80010	10	80000	10	80000	50	640000	1	1	5	20031	20050	20050	3	21	80010	20	80000	20	160000	20050	20059	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10043	8	4	1	21	25	2	1	1	21	21	20047	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	0	0	186	0	44	29	80010	10	80000	10	80000	50	640000	0	1	5	20031	20068	20068	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10045	8	5	1	21	25	2	1	1	21	7	20047	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	0	0	0	0	44	27	80010	10	80000	10	80000	50	640000	1	1	5	20031	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10045	8	6	1	21	25	2	1	1	21	21	20047	20	1	160000	10	20051	20051	20051	20051	20113
160024	20050	150	0	0	0	6	0	159	27	80010	10	80000	10	80000	50	640000	1	1	5	20031	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10045	8	5	1	21	25	2	1	1	18	8	20047	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	151	0	0	0	72	0	44	27	80010	10	80000	10	80000	50	640000	1	1	5	20031	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10031	8	5	1	9	25	2	1	1	21	21	20047	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	150	0	0	0	0	0	44	27	80010	10	80000	10	80000	50	640000	1	1	5	20031	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10032	8	5	1	9	25	2	1	1	7	21	20047	20	1	160000	10	20051	20051	20051	20051	20051
160024	20050	151	0	0	0	0	0	44	27	80010	10	80000	10	80000	50	640000	1	1	5	20031	20050	20050	3	21	80010	20	80000	20	160000	20050	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10045	8	5	1	21	25	2	1	1	21	21	20047	20	1	160000	10	20051	20051	20051	20051	20051

Test 5: throughput

Count: 16

Code:

  sli v0.8h, v16.8h, #3
  sli v1.8h, v16.8h, #3
  sli v2.8h, v16.8h, #3
  sli v3.8h, v16.8h, #3
  sli v4.8h, v16.8h, #3
  sli v5.8h, v16.8h, #3
  sli v6.8h, v16.8h, #3
  sli v7.8h, v16.8h, #3
  sli v8.8h, v16.8h, #3
  sli v9.8h, v16.8h, #3
  sli v10.8h, v16.8h, #3
  sli v11.8h, v16.8h, #3
  sli v12.8h, v16.8h, #3
  sli v13.8h, v16.8h, #3
  sli v14.8h, v16.8h, #3
  sli v15.8h, v16.8h, #3

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40061	299	9	29	25	160108	100	160008	100	160020	500	1280132	1	40019	0	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	61	6	1	1	1	10118	16	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	29	25	160108	100	160008	100	160020	500	1280132	1	40019	0	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	16	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	299	0	504	25	160108	100	160008	100	160020	500	1280132	1	40019	0	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	16	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	301	0	29	25	160108	100	160008	100	160020	500	1280132	1	40019	0	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	16	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	29	25	160108	100	160008	100	160020	500	1280132	1	40019	0	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	16	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	29	25	160108	100	160008	100	160020	500	1280132	1	40019	0	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	153	1	1	1	10118	16	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	299	0	29	25	160108	100	160008	100	160020	500	1280132	1	40019	0	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	16	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	29	25	160108	100	160008	100	160020	500	1280132	1	40019	0	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	16	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	300	0	504	25	160108	100	160008	100	160020	500	1280132	1	40019	0	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	1	1	1	10118	16	40035	160000	100	40039	40039	40039	40039	40039
160204	40038	299	0	29	25	160108	100	160008	100	160020	500	1280132	1	40019	0	40038	40038	19977	6	19989	160120	200	160032	200	320064	40038	40038	1	1	160201	100	99	100	100	160000	100	0	0	2	2	1	10118	16	40035	160000	100	40039	40039	40039	40039	40039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	18	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40050	300	0	0	0	0	0	66	25	160010	10	160000	10	160000	50	1280000	1	1	5	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	8	3	1	5	16	2	1	1	3	4	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	0	45	25	160010	10	160000	10	160000	50	1280000	1	1	5	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	8	4	1	6	16	2	1	1	3	4	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	0	45	25	160010	10	160000	10	160000	50	1280000	1	1	5	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	8	4	1	6	16	2	1	1	7	6	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	299	0	0	0	0	0	45	25	160010	10	160000	10	160000	50	1280000	1	1	5	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	8	4	1	4	16	2	1	1	6	6	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	0	45	25	160010	10	160000	10	160000	50	1280000	1	1	5	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	8	4	1	4	16	2	1	1	7	6	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	0	45	25	160010	10	160000	10	160000	50	1280000	1	1	5	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	8	4	1	4	16	2	1	1	7	4	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	0	45	25	160010	10	160000	10	160000	50	1280000	1	1	5	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	1	0	0	0	0	10022	8	4	1	4	16	2	1	1	7	7	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	0	45	25	160010	10	160000	10	160000	50	1280000	1	1	5	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	8	5	1	4	16	2	1	1	3	4	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	0	45	25	160010	10	160000	10	160000	50	1280000	1	1	5	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	8	5	1	6	16	2	1	1	6	4	40035	20	8	160000	10	40039	40039	40039	40039	40039
160024	40038	300	0	0	0	0	0	45	25	160010	10	160000	10	160000	50	1280000	1	1	5	40019	40038	40038	19996	3	20018	160010	20	160000	20	320000	40038	40038	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	0	10022	8	5	1	6	16	2	1	1	6	4	40035	20	8	160000	10	40039	40039	40039	40039	40039

SLI (vector, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations