Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SMAXP (vector, 4H)

Test 1: uops

Code:

  smaxp v0.4h, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203715006116872510001000100026468020182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
10042037151126116872510001000100026468020182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
1004203715006116872510001000100026468020182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
1004203716006116872510001000100026468020182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
10042037150061168725100010001000264680201820372037157231895100010002000203720371110011000011573216221787100020382038203820382038
1004203715066116872510001000100026468020182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
1004203715036116872510001000100026468020182037203715723189510001000200020372037111001100000073216221787100020382038203820382038
10042037150126116872510001000100026468020182037203715723189510001000200020372037111001100002073216221787100020382038203820382038
1004203716006116872510001000100026468020182037203715723189510001000200020372037111001100001073216221787100020382038203820382038
1004203715006116872510001000100026468020182037203715723189510001000200020372037111001100000073216221787100020382038203820382038

Test 2: Latency 1->2

Code:

  smaxp v0.4h, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000010071011611197914100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000020071011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000010071011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000010071011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000010071011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000010071011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000071011611197910100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100011147071011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000020071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150006119687251001010100001010000502847680200182003720037184440318767100102010000202000020037200371110021109101010000100800640316221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680200182003720037184440318767100102010000202000020037200371110021109101010000100100640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680200182003720037184440318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
10024200371500044119687251001010100001010000502847680200182003720037184440318767100102010000202000020037200371110021109101010000100100640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680200182003720037184440318767100102010000202000020037200371110021109101010000100406640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680200182003720037184440318767100102010000202000020037200371110021109101010000100100640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680200182003720037184440318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680200182003720037184440318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680200182003720037184440318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
1002420037149006119687251001010100001010000502847680200182003720037184440318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  smaxp v0.4h, v1.4h, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371490061196872510100100100001001000050028476800020018200372003718422318745101002001000020020000200372003711102011009910010010000100000710001161119791100001002003820038200382003820038
102042003715010611968725101001001000010010000500284768000200182003720037184223187451010020010000200200002003720037111020110099100100100001000520710001161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800020018200372003718422318745101002001000020020000200372003711102011009910010010000100000710001161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800020018200372003718422318745101002001000020020000200372003711102011009910010010000100020710001161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801020018200372003718422318745101002001000020020000200372003711102011009910010010000100020710001162119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801020018200372003718422318745101002001000020020000200372003711102011009910010010000100000710001161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800020018200372003718422318745101002001000020020000200372003711102011009910010010000100000710001161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801020018200372003718422318745101002001000020020000200372003711102011009910010010000100000710001161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768010200182003720037184223187451010020010000200200002003720037111020110099100100100001000460710001161119791100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801020018200372003718422318745101002001000020020000200372003711102011009910010010000100026710001161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768012001802003720037184563187671001020100002020000200372003711100211091010100001050640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500611968725100221010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768012001802003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768012001832003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  smaxp v0.4h, v8.4h, v9.4h
  smaxp v1.4h, v8.4h, v9.4h
  smaxp v2.4h, v8.4h, v9.4h
  smaxp v3.4h, v8.4h, v9.4h
  smaxp v4.4h, v8.4h, v9.4h
  smaxp v5.4h, v8.4h, v9.4h
  smaxp v6.4h, v8.4h, v9.4h
  smaxp v7.4h, v8.4h, v9.4h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0309181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200581500004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000051103161120035800001002003920039200392003920039
80204200381500004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000010651101161120035800001002003920039200392003920039
80204200381500004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
80204200381500004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
80204200881500004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
80204200381500004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
80204200381500004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
80204200381500004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000010351101161120035800001002003920039200392003920039
80204200381500004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000030051101161120035800001002003920039200392003920039
80204200381500004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000010051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200471500000003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100000050201161120035080000102003920039200392003920039
80024200381500000003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100000050201161120035080000102003920039200392003920039
800242003816300000039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000400350201161120035080000102003920039200392003920039
80024200381500000003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100000350201161120035080000102003920039200392003920039
80024200381500000003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100000050201161120035080000102003920039200392003920039
80024200381500000003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100000050201161120035080000102003920039200392003920039
80024200381500000003925800101080000108000056640000120019200382003899963100188001020800002016000020038200381180021109101080000100000050201161120035080000102003920039200392003920039
80024200381500000003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100000050201161120035080000102003920039200392003920039
80024200381500000003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100012350201161120035080000102003920039200392003920039
80024200381500000003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100000050201161120035080000102003920039200392003920039