Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SMAXP (vector, 4S)

Test 1: uops

Code:

  smaxp v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)033f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203716611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037156116872510001000100026468020182037203715723189510001000200020372037111001100009973116111787100020382038203820382038
10042037151031687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203716611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037161031687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203716611687251000100010002646802018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  smaxp v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715036119687251010010010000100100005002847680020018200372003718429718740101002001000820020016200372003711102011009910010010000100000011171701600198011100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184222518745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
1020420037150366119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000021220000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000000870611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
1002420037150000000010571968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371550000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
100242003715000000007261968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
100242003715000000150611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000060611968725100101010000101000050284768002009020037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  smaxp v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0318191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500018611968725101001001000010010000500284768012001820182200371842231874510100200100002002000020037200371110201100991001001000010007102161119791100001002008720038200382003820038
1020420037150000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
1020420037150009611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9facc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720084111002110910101000010006402162219785010000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
100242003714900611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001820037200371844431876710468201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  smaxp v0.4s, v8.4s, v9.4s
  smaxp v1.4s, v8.4s, v9.4s
  smaxp v2.4s, v8.4s, v9.4s
  smaxp v3.4s, v8.4s, v9.4s
  smaxp v4.4s, v8.4s, v9.4s
  smaxp v5.4s, v8.4s, v9.4s
  smaxp v6.4s, v8.4s, v9.4s
  smaxp v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9facbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420038150061258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000511031611200350800001002003920039200392003920039
80204200381500705258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000511011611200350800001002003920039200392003920039
8020420038150040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000511011611200940800001002003920039200392003920039
8020420038150040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000511011611200350800001002003920039200392003920039
80204200381500126258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000511011611200350800001002003920039200392003920039
8020420038150040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000511011611200350800001002003920039200392003920039
8020420038150040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000511011611200350800001002003920039200392003920039
8020420038150040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000511011611200350800001002003920039200392003920039
8020420038150040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000511011611200350800001002003920039200392003920039
802042003814931840258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000511011611200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)d9ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200391500000000392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010000000502012160221020035080000102003920039200392003920039
8002420038150000040500392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010000000502022160221120035080000102003920039200392003920039
8002420038150000031500392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010000000502022160222220035080000102003920039200392003920039
80024200381500000000392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010000000502022160222220035080000102003920039200392003920039
800242003815000003300039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000000050201116092220035080000102003920039200392003920039
80024200381500000000392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010000000502022160222220035080000102003920039200392003920039
8002420038150000022800392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010000000502022160221120035080000102003920039200392003920039
8002420038150000029400392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010000000502011160222220035080000102003920039200392003920039
8002420038150000000039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000000050202216022920035080000102003920039200392003920039
8002420038150000034800392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010000000502022160101920035080000102003920039200392003920039