Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SMAXP (vector, 8H)

Test 1: uops

Code:

  smaxp v0.8h, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150061168725100010001000264680020182037203715723189510001000200020372037111001100001273116111787100020382038203820382038
10042037150156116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  smaxp v0.8h, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fst unit uop (a7)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715011061196872510100100100001001000050028476801200182003720037184297187401010020010008200200162003720037111020110099100100100001000031117181161119805100001002003820038200382003820038
102042003715011061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007102162219791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007102162219791100001002003820038200382003820038
1020420037150000251196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020210099100100100001000000007102162219791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000100007102162219791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000030007102162219791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007102162219791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007102162219791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000007102162219791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001001000007102162219791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
100242003715096119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100003640216221978510000102003820038200382003820038
10024200371500726196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000154640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100003640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  smaxp v0.8h, v1.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)033f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371506119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100001071011611197910100001002003820038200382003820038
10204200371506119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100002071011611197910100001002003820038200382003820038
10204200371506119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204200371506119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204200371506119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000371011611197910100001002003820038200382003820038
10204200371506119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
102042003715044119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038
10204200371506119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000073911611197910100001002003820038200382003820038
10204200371506119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100001371011611197910100001002003820038200382003820038
10204200371506119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000002400611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382008620038
100242008515000101418801031968725100101010012101000055284896302009020037200371844471876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000102080016402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000003006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
100242003715000300001031968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000100006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038
100242003715000000006941968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000000006402162219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  smaxp v0.8h, v8.8h, v9.8h
  smaxp v1.8h, v8.8h, v9.8h
  smaxp v2.8h, v8.8h, v9.8h
  smaxp v3.8h, v8.8h, v9.8h
  smaxp v4.8h, v8.8h, v9.8h
  smaxp v5.8h, v8.8h, v9.8h
  smaxp v6.8h, v8.8h, v9.8h
  smaxp v7.8h, v8.8h, v9.8h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200491500126258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000051103161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000010351101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200382180201100991001008000010000010351101161120035800001002003920039200392003920039
80204200381501861258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000312051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000010351101161120035800001002003920039200392003920039
802042003815015103258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000010351101161120035800001002003920039200392003920039
80204200381500172258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000010051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000051101161120035800001002003920039200392003920039
8020420038150040258010010080000113800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010000000051101161120035800001002003920039200392003920039
8020420038150040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010000000051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200471500392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010005020231622222003580000102003920039200392003920039
800242003815006025800101080000108000050640000020019200382003899962610018800102080000201600002003820038118002110910108000010005020221622222003580000102003920039200392003920039
800242003815004672580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010005020221611222003580000102003920039200392003920039
800242003815007042580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010005020221622222003580000102003920039200392003920039
80024200381490392580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010005020221622222003580000102003920039200392003920039
80024200381500812580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010005020111622112003580000102003920039200392003920039
80024200381500812580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010005020221622222003580000102003920039200392003920039
800242003815001022580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010005020101622112003580000102003920039200392003920039
8002420038150039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000502022169222003580000102003920039200392003920039
800242003815001232580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010005020111622112003580000102003920039200392003920039