Firestorm: SMAXV (vector, 16B) measurements

Code:

  smaxv b0, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	3a	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	1	1	0	2	68	2547	25	1000	1000	1000	398160	0	3018	3037	3037	2414	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	77	4	16	4	4	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	1	1	0	2	68	2547	25	1000	1000	1000	398160	0	3018	3037	3037	2414	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	77	4	16	4	4	2629	1000	3038	3038	3038	3038	3038
1004	3037	22	1	1	81	2	68	2547	25	1000	1000	1000	398160	0	3018	3037	3037	2414	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	1	0	77	4	16	4	4	2629	1000	3038	3038	3038	3085	3038
1004	3037	23	1	1	0	2	68	2547	25	1000	1000	1000	398160	0	3018	3037	3037	2414	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	3	77	4	16	4	4	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	1	1	0	2	68	2547	25	1000	1000	1000	398160	0	3018	3037	3037	2414	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	77	4	16	4	4	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	1	1	0	2	68	2547	25	1000	1000	1000	398160	0	3018	3037	3037	2414	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	77	4	16	4	4	2629	1000	3038	3038	3038	3038	3038
1004	3037	22	1	1	0	2	68	2547	25	1000	1000	1000	398160	0	3018	3037	3037	2414	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	77	4	16	4	4	2629	1000	3038	3038	3038	3038	3038
1004	3037	22	1	1	0	2	187	2547	25	1000	1000	1000	398160	0	3018	3037	3037	2414	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	77	4	16	4	4	2629	1000	3084	3038	3038	3038	3038
1004	3037	23	1	1	0	2	68	2547	25	1000	1000	1000	398160	0	3018	3037	3037	2414	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	77	4	16	4	4	2629	1000	3038	3038	3038	3038	3038
1004	3037	23	1	1	0	2	68	2547	25	1000	1000	1000	398160	0	3018	3037	3037	2414	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	77	4	16	4	4	2629	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->2

Code:

  smaxv b0, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	114	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	0	30037	30037	28264	3	28745	10272	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	243	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30065	0	30037	30037	28264	3	28745	10100	200	10180	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29633	0	10000	100	30038	30038	30038	30038	30085
10204	30037	225	0	160	29547	25	10100	100	10000	100	10000	500	4277160	30018	0	30037	30037	28264	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	12	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	0	30037	30037	28264	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29633	0	10000	100	30085	30038	30038	30038	30038
10204	30037	225	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	0	30037	30037	28264	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	739	1	16	1	1	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	0	30037	30037	28264	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	114	29547	25	10100	100	10000	100	10000	500	4277160	30018	3	30037	30037	28264	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	0	30037	30037	28264	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	0	30037	30037	28264	3	28745	10100	200	10000	200	20000	30037	30037	3	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29633	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29547	25	10100	100	10000	100	10000	500	4277160	30018	0	30037	30037	28264	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29633	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	241	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30228	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30085	30037	28299	3	28767	10010	20	10180	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20322	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	3	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	3526	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30085	30037	28286	3	28767	10010	20	10000	20	20000	30135	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038

Test 3: throughput

Count: 8

Code:

  smaxv b0, v8.16b
  smaxv b1, v8.16b
  smaxv b2, v8.16b
  smaxv b3, v8.16b
  smaxv b4, v8.16b
  smaxv b5, v8.16b
  smaxv b6, v8.16b
  smaxv b7, v8.16b

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80204	20061	150	0	0	0	0	15	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	160064	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	1	1	1	5118	1	16	1	1	20036	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	0	0	0	0	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80344	200	160064	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	1	1	1	5118	1	16	1	1	20036	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	1	0	0	0	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	160064	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	1	1	1	5118	1	16	1	1	20036	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	0	0	0	204	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	160064	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	1	1	1	5118	1	16	1	1	20036	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	0	0	0	0	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	160064	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	1	1	1	5118	1	16	1	1	20036	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	0	0	0	0	0	170	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80425	200	80032	200	160064	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	1	1	1	5118	1	16	1	1	20036	80000	100	20040	20040	20040	20040	20040
80204	20039	150	0	0	0	0	0	0	30	25	80108	100	80008	100	80020	500	640132	0	20182	20039	20039	9977	6	9990	80120	200	80032	200	160064	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	1	1	1	5118	1	16	1	1	20036	80000	100	20040	20107	20040	20040	20040
80204	20039	150	0	0	0	0	0	0	30	25	80108	100	80008	100	80020	500	640132	0	20020	20039	20039	9977	6	9990	80120	200	80032	200	160064	20039	20039	1	1	80201	100	99	100	100	80000	100	0	0	0	2	2	2	5129	2	23	2	2	20046	80000	100	20049	20049	20049	20050	20049
80204	20049	150	0	0	0	0	0	0	64	26	80116	100	80016	100	80028	500	640196	0	20029	20048	20048	9976	10	9986	80128	200	80038	200	160076	20048	20049	1	1	80201	100	99	100	100	80000	100	0	0	0	2	2	2	5128	2	23	2	3	20046	80000	100	20049	20049	20050	20050	20049
80204	20048	150	0	0	0	0	0	0	64	26	80116	100	80016	100	80028	500	640196	0	20029	20048	20048	9976	9	9986	80128	200	80038	200	160076	20048	20048	1	1	80201	100	99	100	100	80000	100	0	0	0	2	2	2	5128	2	23	2	2	20045	80000	100	20050	20049	20049	20049	20050

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d2	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	df	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
80024	20050	155	0	0	0	40	25	80010	10	80000	10	80000	50	640000	0	1	20020	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5022	1	4	16	0	5	5	2	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	27	40	25	80010	10	80000	10	80104	50	640000	0	1	20060	20131	20142	10015	6	10073	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5022	0	3	16	0	3	5	2	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	0	40	25	80010	10	80000	10	80000	50	640000	0	1	20020	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	9	0	0	5022	0	5	16	0	3	5	2	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	0	40	25	80010	10	80000	10	80000	50	640000	0	1	20020	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5022	0	3	16	0	7	5	2	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	0	40	25	80010	10	80000	10	80000	50	640000	0	1	20020	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5022	0	2	16	0	3	2	2	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	0	40	51	80010	10	80000	10	80000	50	640000	0	1	20020	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5022	0	2	16	0	6	5	2	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	0	40	25	80010	10	80000	10	80000	50	640000	0	1	20020	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	1	5022	0	2	16	0	5	3	2	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	0	40	25	80010	10	80000	10	80000	50	640000	0	1	20020	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5022	0	5	16	0	5	3	2	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	12	40	25	80010	10	80000	10	80000	50	640000	0	1	20020	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5022	0	5	16	0	3	3	2	20036	80000	10	20040	20040	20040	20040	20040
80024	20039	150	0	0	0	40	25	80010	10	80000	10	80000	50	640000	0	1	20020	20039	20039	9996	3	10019	80010	20	80000	20	160000	20039	20039	1	1	80021	10	9	10	10	80000	10	0	0	0	0	0	0	5022	0	5	16	0	5	5	2	20036	80000	10	20040	20040	20040	20040	20040

SMAXV (vector, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations