Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SMAXV (vector, 8H)

Test 1: uops

Code:

  smaxv h0, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372306125472510001000100039816013018303730372414328951000100020003037303711100110000073216222629100030383038303830383038
100430372306125472510001000100039816003018303730372414328951000100020003037303711100110001073216222629100030383038303830383038
100430372306125472510001000100039816003018303730372414328951000100020003037303711100110000073116222629100030383038303830383038
100430372206125472510001000100039816013018303730372414328951000100020003037303711100110000073216222629100030383038303830383038
100430372306125472510001000100039816013018303730372414328951000100020003037303711100110000073216222629100030383038303830383038
1004303722021025472510001000100039816003018303730372414328951000100020003037303711100110000073216222629100030383038303830383038
100430372206125474310001000100039816013018303730372414328951000100020003037303711100110000073216222629100030383038303830383038
100430372306125472510001000100039816013018303730372414328951000100020003037303711100110000073216222629100030383038303830383038
100430372306125472510001000100039816003018303730372414328951000100020003037303711100110000073216222629100030383038303830383038
100430372306125472510001000100039816003018303730372414328951000100020003037303711100110000073216222629100030383038303830383038

Test 2: Latency 1->2

Code:

  smaxv h0, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0318191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037224000061295472510100100100001001000050042771600300183003730037282643287451010020010000200200003003730037111020110099100100100001000071021611296330100001003003830038300383003830038
1020430037224000061295472510100100100001001000050042771600300183003730037282643287451010020010000200200003003730037111020110099100100100001000071011611296330100001003003830038300383003830038
1020430037225000061295472510100100100001001000050042771601300183003730037282643287451010020010000200200003003730037111020110099100100100001000071011611296330100001003003830038300383003830038
1020430037225000061295472510100100100001001000050042771600300183003730037282643287451010020010000200200003003730037111020110099100100100001000071011611296330100001003003830038300383003830038
1020430037225000061295472510100100100001001000050042771600300183003730037282643287451010020010000200200003003730037111020110099100100100001000071011611296330100001003003830038300383003830038
1020430037225000061295472510100100100001001000050042771600300183003730037282643287451010020010000200200003003730037111020110099100100100001000071011611296330100001003003830038300383003830038
1020430037225000061295472510100100100001001000050042771600300183003730037282643287451010020010000200200003003730037111020110099100100100001000071011611296330100001003003830038300383003830038
10204300372250000726295472510100100100001001000050042771600300183003730037282643287451010020010000200200003003730037111020110099100100100001000071011611296330100001003003830038300383003830038
10204300372250000726295472510100100100001001000050042771600300183003730037282643287451010020010000200200003003730037111020110099100100100001000071011611296330100001003003830038300383003830083
10204300372250000103295472510100100100001001000050042771600300183003730037282643287451010020010000200200003003730037111020110099100100100001000071011611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250612954725100101010000101000050427716030018300373003728286328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038
100243003722505272954725100101010000101000050427716030018300373003728300328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038
100243003722402082954725100101010000101000050427716030018300373003728286328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038
100243003722503762954725100101010000101000050427716030018300373003728286328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038
10024300372250612954725100101010000101000050427716030018300373003728286328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038
100243003722501702954725100101010000101000050427716030018300373003728286328767100102010000202034430037300371110021109101010000100000640216222962910000103003830038300383003830038
100243003722505702954725100101010000101000050427716030018300373003728286328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038
10024300372250612954725100101010000101000050427716030018300373003728286328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038
100243003722404632954725100101010000101000050427716030018300373003728286328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038
100243003722501072954725100101010000101000050427716030018300373003728286328767100102010000202000030037300371110021109101010000100000640216222962910000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  smaxv h0, v8.8h
  smaxv h1, v8.8h
  smaxv h2, v8.8h
  smaxv h3, v8.8h
  smaxv h4, v8.8h
  smaxv h5, v8.8h
  smaxv h6, v8.8h
  smaxv h7, v8.8h
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0318191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200611500000512580108100800081008002050064013202002020039200399977699908012020080032200160064200392003911802011009910010080000100000000111511811620036800001002004020040200402004020040
802042003915000003025801081008000810080020500640132020020200392003999776100248012020080032200160064200392003911802011009910010080000100000000111511801620036800001002004020040200402004020040
80204200391500000302580108100800081008002050064013202002020039200399977699908012020080032200160064200392003911802011009910010080000100000000111511801620036800001002004020040200402004020040
80204200391500000302580108100800081008002050064013212002020039200399977699908012020080032200160064200392003911802011009910010080000100000000111511801620036800001002004020040200402004020040
80204200391500000532580108100800081008002050064013202002020039200399977699908012020080032200160064200392003911802011009910010080000100000100111511801620036800001002004020040200402004020040
80204200391500000512580108100800081008002050064013212002020039200399977699908012020080032200160064200392003911802011009910010080000100000000111511801620036800001002004020040200402004020040
802042008915000001352580108100800081008002050064013202002020039200399977699908012020080032200160064200392003911802011009910010080000100000000111511801620036800001002004020040200402004020040
80204200391500000302580108100800081008002050064013202002020039200399977699908012020080032200160064200392003911802011009910010080000100000000111511801620036800001002004020040200402004020040
802042003915000001252580108100800081008002050064013202002020039200399977699908012020080032200160064200392003911802011009910010080000100000100111511801620036800001002004020040200402004020040
80204200391500000302580108100800081008002050064013202002020039200399977699908012020080032200160064200392003911802011009910010080000100000000111511801620036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03181e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)d9ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200501500000126258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000050209160632003680000102004020040200402004020040
8002420039150000040258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000050202160422003680000102004020040200402004020040
80024200391500000359258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001000050202160242003680000102004020040200402004020040
8002420039150000082258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001010050204160422003680000102004020040200402004020040
800242003915000021170258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001000050204160242007780000102004020040200402004020040
8002420039150000040258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000050203160422003680000102004020040200402004020040
80024200391500300322258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001000050204160242003680000102004020040200402004020040
8002420039150000040258001010800001080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001010050205160652003680000102004020040200402004020040
8002420039150000061258001010800981080000506400000200202003920039999631001980010208000020160000200392003911800211091010800001000050203160242003680000102004020040200402004020040
80024200391560000497258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000050204160422009780000102004020040200402004020040