Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SMAX (vector, 16B)

Test 1: uops

Code:

  smax v0.16b, v0.16b, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037150611687251000100010002646800201820372037157231895100010002000203720371110011000073216111787100020382038203820382038
10042037160611687251000100010002646800201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037150611687251000100010002646800201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037150611687251000100010002646801201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037150611687251000100010002646801201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037150821687251000100010002646801201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
100420371501561687251000100010002646800201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037156611687251000100010002646801201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037150611687251000100010002646800201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037150611687251000100010002646801201820372037157231895100010002000203720371110011000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  smax v0.16b, v0.16b, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500061196872510100100100001001000050028476801200182003720037184290718740101002001000820020016200372003711102011009910010010000100001117181619801100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184290718741101002001000820020016200372003711102011009910010010000100131117171619801100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200182003720037184290718741101002001000820020016200372003711102011009910010010000100001117171619802100001002003820038200382003820038
102042003715000193196872510100100100001001000050028476800200182003720037184290718741101002001000820020016200372003711102011009910010010000100001117181619801100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200182003720037184290618740101002001000820020016200372003711102011009910010010000100001117171619801100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476801200182003720037184290618740101002001000820020016200372003711102011009910010010000100001117181619801100001002003820038200382003820038
10204200371500061196872510100100100001001000050028476800200182003720037184290718741101002001000820020016200372003711102011009910010010000100001117181619802100001002003820038200382003820038
102042003715000996196872510100100100001001000050028476800200182003720037184290718740101002001000820020016200372003711102011009910010010000100001117181619802100001002003820038200382003820038
1020420037150021726196872510100100100001001000050028476801200182003720037184290718740101002001000820020016200372003711102011009910010010000100001117181619802100001002003820038200382003820038
1020420037150001545196872510100100100001001000050028476800200182003720037184290718741101002001000820020016200372003711102011009910010010000100001117181619802100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
10024200371500000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000156402162219785010000102003820038200382003820038
1002420037150000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
1002420037150000061196872510026101001212100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000036402162219785010000102003820038200382003820038
1002420037150000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
1002420037150000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000066402162219785010000102003820038200382003820038
10024200371500000536196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
1002420037150000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
1002420037150000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038
1002420037150000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000006402162219785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  smax v0.16b, v1.16b, v0.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)st unit uop (a7)l1d cache writeback (a8)acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000611968725101001001000010010000500284768012001820037200371842203187451010020010000200203602003720037111020110099100100100001000003017102161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001820037200371842203187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001820037200371842203187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422031874510100200100002002000020037200371110201100991001001000010000018007101161119791100001002003820038200382003820038
1020420037150005811968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000010007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680120018200372003718422031874510268200100002002000020085200372110201100991001001000010000012007101161119827100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001002113007321161119823100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000010007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768012001820037200371842203187451010020010000200200002003720037111020110099100100100001000000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03181f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010021640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001009640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001003640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000536196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001006640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010012640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  smax v0.16b, v8.16b, v9.16b
  smax v1.16b, v8.16b, v9.16b
  smax v2.16b, v8.16b, v9.16b
  smax v3.16b, v8.16b, v9.16b
  smax v4.16b, v8.16b, v9.16b
  smax v5.16b, v8.16b, v9.16b
  smax v6.16b, v8.16b, v9.16b
  smax v7.16b, v8.16b, v9.16b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)033a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042005815004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000030511021611200350800001002003920039200392003920039
802042003815018225801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000100511011611200350800001002003920039200392003920039
802042003815004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000030511011611200350800001002003920039200392003920039
80204200381500612580100100800001008000050064000002001920038200389973399968010020080000200160000200382003811802011009910010080000100201140511011611200350800001002003920039200392003920039
802042003815004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000100511011611200350800001002003920039200392003920039
802042003815004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000130511011611200350800001002003920039200392003920039
802042003815004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000511011611200350800001002003920039200392003920039
80204200381500402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100002190511011611200350800001002003920039200392003920039
802042003815004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000511011611200350800001002003920039200392003920039
802042003815004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000000511011611200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200471500039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001044305020416422003580000102003920039200392003920039
80024200381500039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001037605020416422003580000102003920039200392003920039
8002420038150013925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100005020316422003580000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100005020216442003580000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100005020216422003580000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100005020216422003580000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100305020416422003580000102003920039200392003920039
80024200381500039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001001205020416242003580000102003920039200392003920039
8002420038150003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100005020216422003580000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000101305020216422003580000102003920039200392003920039