Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SMAX (vector, 4S)

Test 1: uops

Code:

  smax v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)191e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037150096116872510001000100026468002018203720371572318951000100020002037203711100110000073216111787100020382038203820382038
10042037150006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150006116872510001000100026468002018203720371572318951000100020002037203711100110004073116111787100020382038203820382038
10042037150006116872510001000100026468002018203720371572318951000100020002037203711100110000673116111787100020382038203820382038
10042037150006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150008216872510001000100026468002018203720371572318951000100020002037203711100110000373116111787100020382038203820382038
10042037150006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037160006116872510001000100026468002018203720371572318951000100020002037203711100110006073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  smax v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204200371500611968725101001001000010010000500284768020018020037200371842231874510100200100002002000020037200371110201100991001001000010000078411611197910100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768020018020037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200841500611968725101001001000010010000500284768020018020037200371842231874510100200100002002000020037200371110201100991001001000010000271011611197910100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768020018020037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768020018020037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768020018020037200371843531874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768020018020037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768020018020037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371509611968725101001001000010010000500284768020018020037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768020018020037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5e60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500611968725100101010000101000050284768001200182003720037184443187671001020100002020000200372003711100211091010100001001080640216221978510000102003820038200382003820038
1002420037150061196872510010101000010100005028476800120018200372003718444318767100102010000202000020037200371110021109101010000100964665224221982310000102003820084200862003820038
1002420037150014519687251001012100001010152502847680012001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
100242003715012611968725100101010000101000050284768001200182003720037184443187671001020100002020000200372003711100211091010100001001170640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680012001820037200371844431876710010201000020200002003720037111002110910101000010100640216221978510000102003820038200382008520038
100242003715006119687251001010100001010000502847680012001820037200371844431876710010201000020200002003720037111002110910101000010077230640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680012001820037200371844431876710010201000020200002003720037111002110910101000010020960640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768001200182003720037184443187671001020100002020000200372003711100211091010100001001530640216221978510000102003820038200382003820038
100242003714906119687251001010100001010000502847680012001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680012001820037200371844431876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  smax v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000317101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100059307101161119791100001002003820038200382003820038
1020420037150115611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000307101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000307101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000307101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150000000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000040006402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002210910101000010000180306402162219785010000102003820038200382003820038
1002420037150000000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
1002420037150000000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038
1002420037150000000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000906402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000370306402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000380306402162219785010000102003820038200382003820038
10024200371500000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000370006402162219785010000102003820038200382003820038
1002420037150000000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000006402162319785010000102003820038200382003820038
1002420037150000000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000006402162219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  smax v0.4s, v8.4s, v9.4s
  smax v1.4s, v8.4s, v9.4s
  smax v2.4s, v8.4s, v9.4s
  smax v3.4s, v8.4s, v9.4s
  smax v4.4s, v8.4s, v9.4s
  smax v5.4s, v8.4s, v9.4s
  smax v6.4s, v8.4s, v9.4s
  smax v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0309191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042005715000040258010010080000100800005006400000200192003820038997339996801002008000020016000020038200381180201100991001008000010002803051103161120035800001002003920039200392003920039
80204200381500004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000500051101161120035800001002003920039200392003920039
802042003815000040258010010080000100800005006400001200192003820038997339996801002008000020016000020038200381180201100991001008000010003503051101161120035800001002003920039200392003920039
8020420038150000402580100100800001008000050064000012001920038200389973310021801002008000020016000020038200381180201100991001008000010000066051271161120035800001002003920039200392003920039
80204200381500004025801001008000010080000500640764020019200382003899733999680199200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
80204200381500006325801001008000011380095500640000120019200382003899733100228030620080000200160000200382003811802011009910010080000100010513051101161120035800001002003920039200392003920039
80204200381560004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000051101161120035800001002003920039200392003920039
80204200381500004025801001008000010080000500640000020019200382003899733999680100200800002001600002003820038118020110099100100800001000100051101161120035800001002003920039200392003920039
802042003815000040258010010080000100800005006400000200192003820038997331002280215200800002001600002003820089118020110099100100800001000006051101161220035800001002003920039200392009520096
80204200381500014721625801001008009410080000500642296020019200382003899733999680100200800002001600002003820038118020110099100100800001000303451101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0318191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004715002029225800101080000108000050640000012001920038200389996310018800102080000201600002003820038118002110910108000010000605020416242003580000102003920039200392003920039
8002420038150000392580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000005020416422003580000102003920039200392003920039
8002420038150000392580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000035020216242003580000102003920039200392003920039
8002420038150000392580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001000005020416422003580000102003920039200392003920039
80024200381500004192580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000005020216242003580000102003920039200392003920039
8002420038150000392580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001000035020216442008380000102003920039200392003920039
8002420038150000392580010108000010800005064000001200192003820038999631001880010208000020160000200382003811800211091010800001000005020416422003580000102003920039200392003920039
8002420038150000392580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001001095020216242003580000102003920039200392003920039
80024200381500002292580010108000010800005064000000200192003820038999631001880010208000020160000200382003811800211091010800001000035020416242003580000102003920039200392003920039
80024200381500003925800101080000108000050640000002001920038200389996310018800102080000201600002003820038118002110910108000010001575020416242003580000102003920039200392003920039