Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SMAX (vector, 8B)

Test 1: uops

Code:

  smax v0.8b, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037150611687251000100010002646800201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037150611687251000100010002646800201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037150821687251000100010002646800201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
100420371515611687251000100010002646801201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037150611687251000100010002646800201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037150611687251000100010002646801201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037159611687251000100010002646801201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037150611687251000100010002646800201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037150611687251000100010002646800201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037150611687251000100010002646801201820372037157231895100010002000203720371110011000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  smax v0.8b, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715006619687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007102172219791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007103162219791100001002003820038200382003820038
1020420037150072519687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100007102162219791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007102162219791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500000000001031968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006403162219823010000102003820038200382003820038
1002420037150000000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
100242003715000000000010271968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006642162219785010000102003820038200382003820038
1002420037150000000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
10024200371500000000001261968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
100242003715000000002310611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402162519785010000102003820038200382003820038
1002420037150000000060611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000036402162219785010000102003820038200382003820038
1002420037150000000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
10024200371500000000007261968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038
10024200371500000000630611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000006402162219785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  smax v0.8b, v1.8b, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150000013217661196872510100100100001001000050028476801200182003720037184297187411010020010008200200162003720037111020110099100100100001000000011171711631198010100001002003820038200382003820038
102042003715000003061196872510100100100001001000050028476801200182003720037184297187411010020010000200200002003720037111020110099100100100001000000000071021622197910100001002003820038200382003820038
102042003715000100061196872510100100100001001000050028476800200182003720037184223187451010020410000200200002003720037111020110099100100100001000000000071021622197910100001002003820038200382003820038
102042003714900003061196872510100100100001001000062028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000071021622197910100001002003820038200382003820038
1020420037150000099061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000071021622197910100001002003820038200382003820226
10204200371500000150124196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000071021624197910100001002003820038200382003820038
1020420037150000015061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000071021622197910100001002003820038200382003820038
102042003715000000061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001002000000071021622197910100001002003820038200382003820038
1020420037150000018061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000071021622197910100001002003820038200382003820038
10204200371500000300156196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001000000000071021622197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0318191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
100242003715000129251196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
100242003715000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
100242003715000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000030640216221978510000102003820038200382003820086
100242003715000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
100242003715000061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
100242003715000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
10024200371500018361196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
10024200371500028261196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038
100242003715000061196872510010101000010100005028476800200182003720037184443187671001020100002020000200372003711100211091010100001000000640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  smax v0.8b, v8.8b, v9.8b
  smax v1.8b, v8.8b, v9.8b
  smax v2.8b, v8.8b, v9.8b
  smax v3.8b, v8.8b, v9.8b
  smax v4.8b, v8.8b, v9.8b
  smax v5.8b, v8.8b, v9.8b
  smax v6.8b, v8.8b, v9.8b
  smax v7.8b, v8.8b, v9.8b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l1i tlb fill (04)181e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fa9accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042005815000004025801001008000010080000500640000102001902003820038997339996801002008000020016000020038200381180201100991001008000010000511003161220035800001002003920039200392003920039
802042003815000004025801001008000010080000500640000002001902003820038997339996801002008000020016000020038200381180201100991001008000010000511001161120035800001002003920039200392003920039
802042003815000004025801001008000010080000500640000102001902003820038997339996801002008000020016000020038200381180201100991001008000010000511001161120035800001002003920039200392003920039
802042003815000004025801001008000010080000500640000152001902003820038997339996801002008000020016000020038200381180201100991001008000010000511001161120035800001002003920039200392003920039
8020420038150000051525801001008000010080000500640000002001902003820038997339996801002008000020016000020038200381180201100991001008000010000511051161120035800001002003920039200392003920039
802042003815000004025801001008000010080000500640000152001902003820038997339996801002008000020016000020038200381180201100991001008000010000511001161120035800001002003920039200392003920039
8020420038150001504025801001008000010080000500640000152001902003820038997339996801002008000020016000020038200381180201100991001008000010000511001161120035800001002003920039200392003920039
802042003815000004025801001008000010080000500640000002001902003820038997339996801002008000020016000020038200381180201100991001008000010000511051161120035800001002003920039200392003920039
802042003815000004025801001008000010080000500640000152001902003820038997339996801002008000020016000020038200381180201100991001008000010000511051161120035800001002003920039200392003920039
8020420038150001504025801001008000010080000500640000002001902003820038997339996801002008000020016000020038200381180201100991001008000010000511051161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420039150003925800101080000108000050640000102001920038200389996310018800102080000201600002003820038118002110910108000010100502050051600034200350080000102003920039200392003920039
8002420038150003925800101080000108000050640000152001920038200389996710044800102080000201600002009720097118002110910108000010030502054041600043200350080000102003920039200892003920039
80024200381501503925800101080000108000050640000152001920038200389996310018800102080000201600002003820038118002110910108000010000502254031600034200350080000102003920039200392003920039
8002420038150003925800101080000108000050640000152001920038200389996310018800102080000201600002003820038118002110910108000010000502054041600064200350080000102003920039200392003920039
8002420038150003925800101080000108000050640000152001920038200389996310018800102080000201600002003820038118002110910108000010000502054031600044200350080000102003920039200392003920039
8002420038150003925800101080000108000050640000152001920038200389996310018800102080000201600002003820038118002110910108000010000502054061600076200350080000102003920039200392003920039
80024200381500012325800101080000108000050640000152001920038200389996310018800102080000201600002003820038118002110910108000010000502054061600076200350080000102003920039200392003920039
80024200381500060925800101080000108000050640000152001920038200389996310018800102080000201600002003820038118002110910108000010000502054071600076200350080000102003920039200392003920039
8002420038150003925800101080000108000050640000152001920038200389996310018800102080000201600002003820038118002110910108000010000502054061600046200350080000102003920039200392003920039
80024200381500039258001010800001080000506400000520019200382003899963100188001020800002016000020038200381180021109101080000100005022551316200662003520080000102003920039200392003920039