Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SMINP (vector, 16B)

Test 1: uops

Code:

  sminp v0.16b, v0.16b, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000073216111787100020382038203820382038
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203716006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110003073116111787100020382038203820382038
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715096116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203716006116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203716007516872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  sminp v0.16b, v0.16b, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)033f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715018719687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371506119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371506119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715063119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100067101161119791100001002003820038200382003820038
10204200371506119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371506119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101164119791100001002003820038200382003820038
10204200371506119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
10204200371506119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820083
10204200371506119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715081419687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715012611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768002001820037200371844431876710010201000020203362003720084111002110910101000010640216221978510000102003820038200382003820038
100242003715004411968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010640216221978510000102003820038200382003820038
100242003715009091968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010640216221978510000102003820038200382003820038
100242003715002511968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010640216221978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  sminp v0.16b, v1.16b, v0.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
10204200371500000073919687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
1020420037150000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
1020420037150000006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161019791100001002003820038200382003820038
1020420037150000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820085200382003820038
102042003715000000111719687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
1020420037150000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
1020420037150000006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
1020420037150000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038
1020420037150000006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)09191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010006404162219785010000102003820038200382003820038
1002420037150000000611966725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
10024200371500000003741968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
10024200371500000004561968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010006402242319785010000102003820038200382003820038
1002420037150000000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
1002420037150000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
10024200371500000002731968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
1002420037150000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
1002420037150000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010006402482219785010000102003820038200382003820038
1002420037150000000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  sminp v0.16b, v8.16b, v9.16b
  sminp v1.16b, v8.16b, v9.16b
  sminp v2.16b, v8.16b, v9.16b
  sminp v3.16b, v8.16b, v9.16b
  sminp v4.16b, v8.16b, v9.16b
  sminp v5.16b, v8.16b, v9.16b
  sminp v6.16b, v8.16b, v9.16b
  sminp v7.16b, v8.16b, v9.16b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200601500402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051103162220035800001002003920039200392003920039
80204200381500402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051102162220035800001002003920039200392003920039
80204200381500682580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051102162220035800001002003920039200392003920039
80204200381500402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051102162220035800001002003920039200392003920039
80204200381500402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051102292220035800001002003920039200392003920039
80204200381500942580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051102162220035800001002003920039200392003920039
80204200381500402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051102162220035800001002003920087200392003920039
80204200381500612580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051102162220035800001002003920039200392003920039
80204200381500402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051102162220035800001002003920039200392003920039
80204200381500402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000051102162220035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200481500003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100050203168420035080000102003920039200392003920039
80024200381500003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100050204163420035080000102003920039200392003920039
80024200381500003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100050203162320035080000102003920039200392003920039
80024200381500003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100050205164520035080000102003920039200392003920039
80024200381500003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100050203165520035080000102003920039200392003920039
80024200381500003925800101080000108000060640000020019200382003899963100188001020800002016000020038200381180021109101080000100050544164420035080000102003920039200392003920039
80024200381500003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100050204164420035080000102003920039200392003920039
80024200381500003925800101080000108000050640000020019200382003899963100188001020800002016000020038200381180021109101080000100050204164420035080000102003920039200392003920039
80024200381500003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100050205165520035180000102003920039200392003920039
800242003815000123925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100050204165520035080000102003920039200392003920039