Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SMINP (vector, 4S)

Test 1: uops

Code:

  sminp v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715010316872510001000100026468002018203720371572318951000100020002037203711100110001073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000673116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  sminp v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715008521968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071001161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071001161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071001161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071001161119791100001002003820038200382003820038
10204200371500841968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071001161119791100001002003820038200382003820038
10204200371500611968725101001181000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071001161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000071001161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071001161119791100001002003820038200382003820038
102042003715001661968725101001001000010010000500284768002001820037200371842231874510100200101642002000020037200371110201100991001001000010000071001161119791100001002003820038200382003820038
102042003715002081968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000071001161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)033f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715084196872510010101000010100005028476801200182003720037184440318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200862003820038
100242003715061196872510010101000010100005028476801200182003720037184440318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
100242003715061196872510010101000010100005028476801200182003720037184440318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
100242003715061196872510010101000010100005028476800200182003720037184440318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
100242003715061196872510010101000010100005028476801200182003720037184440318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
100242003715084196872510010101000010100005028476801200182003720037184440318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
100242003715061196872510010101000010100005028476801200182003720037184440318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
100242003715061196872510010101000010100005028476801200182003720037184440318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
1002420037150726196872510010101000010100005028476801200182003720037184447318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
100242003715061196872510010101000010100005028476801200182003720037184440318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  sminp v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150186119687251010010010000100100005002847680020018200372003718422031874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
1020420037150216119687251010010010000100100005002847680020018200372003718422031874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
1020420037150216119687251010010010000100100005002847680020018200372003718422031874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422031874510100200100002002000020037200371110201100991001001000010000037101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422031874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042008415096119687251010010010000100100005002847680120018200372003718422031874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422031874510100200100002002000020037200371110201100991001001000010000207101161119791100001002003820038200382003820038
1020420037150276119687251010010010000100100005002847680120018200372003718422031874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680120018200372003718422031874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
1020420037150426119687251010010010000100100005002847680120018200372003718422031874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500006119687251001010100001010000502847680120018200372003718444031876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680120018200372003718444031876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680020018200372003718444031876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680020018200372003718444031876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680020018200372003718444031876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680020018200372003718444031876710010201000020200002003720084111002110910101000010000640216221978510000102003820038200382003820038
100242003715000072619687251001010100001010000502847680020018200372003718444031876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
1002420037150063526119687251001010100001010000502847680020018200372003718444031876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
10024200371500006119687251001010100001010000502847680020018200372003718444031876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038
10024200371500306119687251001010100001010000502847680020018200372003718444031876710010201000020200002003720037111002110910101000010000640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  sminp v0.4s, v8.4s, v9.4s
  sminp v1.4s, v8.4s, v9.4s
  sminp v2.4s, v8.4s, v9.4s
  sminp v3.4s, v8.4s, v9.4s
  sminp v4.4s, v8.4s, v9.4s
  sminp v5.4s, v8.4s, v9.4s
  sminp v6.4s, v8.4s, v9.4s
  sminp v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042003815015402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100051102161120035800001002003920039200392003920039
80204200381500402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
80204200381500402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
80204200381500402580100100800001008000050064076412001920038200389973399968010020080000200160000200382003811802011009910010080000100051281161120035800001002003920039200392003920039
8020420038150279402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
80204200381500402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
80204200381500402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
802042003815036402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
8020420038150273402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039
80204200381500402580100100800001008000050064000012001920038200389973399968010020080000200160000200382003811802011009910010080000100051101161120035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200391500483925800101280000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100005020716422003580000102003920039200392003920039
80024200381500153925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100005020416442003580000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100005020416242003580000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100005020616362003580000102003920039200392008920039
8002420038150003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100005020216442003580000102003920039200392003920039
8002420038150093925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100005020416432003580000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100005020216642003580000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100005020416422003580000102003920039200392003920039
80024200381500153925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000100005020416242003580000102003920039200392003920039
80024200381500123925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000102005020416242003580000102003920039200392003920039