Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SMINV (vector, 8H)

Test 1: uops

Code:

  sminv h0, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303722006125472510001000100039816013018303730372414328951000100020003037303711100110000073316332629100030383038303830383038
1004303723006125472510001000100039816013018303730372414328951000100020003037303711100110000073216332629100030383038303830383038
100430372200612547251000100010003981601301830373037241432895100010002000303730371110011000015073316332629100030383038303830383038
1004303723006125472510001000100039816013018303730372414328951000100020003037303711100110000073316332629100030383038303830383038
1004303722006125472510001000100039816013018303730372414328951000100020003037303711100110000073316332629100030383038303830383038
1004303722006125472510001000100039816013018303730372414328951000100020003037303711100110000073316332629100030383038303830383038
1004303722006125472510001000100039816013018303730372414328951000100020003037303711100110000073316332629100030383038303830383038
1004303722006125472510001000100039816003018303730372414328951000100020003037303711100110000073216232629100030383038303830383038
1004303722006125472510001000100039816003018303730372414328951000100020003037303711100110000073316332629100030383038303830383038
1004303723006125472510001000100039816013018303730372414328951000100020003037303711100110000073316332629100030383038303830383038

Test 2: Latency 1->2

Code:

  sminv h0, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722502662954725101001001000010010000500427716003001803003730037282643287451010020010000200200003003730037111020110099100100100001000007101161129633100001003003830038300383003830038
10204300372250612954725101001001000010010000500427716003001803003730037282643287451010020010000200200003003730037111020110099100100100001000007101161129633100001003003830038300383003830038
10204300372250612954725101001001000010010000500427716013001803003730037282643287451010020010000200200003003730037111020110099100100100001000007101161129780100001003003830038300383003830038
10204300372240612954725101001001000010010000500427716003001803003730037282643287451010020010000200200003003730037111020110099100100100001000007101161129633100001003003830038300383003830038
10204300372250612954725101001001000010010000500427716003001803003730037282643287451010020010000200200003003730037111020110099100100100001000007101161129633100001003003830038300383003830038
10204300372250612954725101001001000010010000500427716003001803003730037282643287451010020010000200200003003730037111020110099100100100001000007101161129633100001003003830038300383003830038
10204300372250612954725101001001000010010000500427716003001803003730037282643287451010020010000200200003003730037111020110099100100100001000007101161129633100001003003830038300383003830038
10204300372250612954725101001001000010010000500427716003001803003730037282643287451010020010000200200003003730037111020110099100100100001000007101161129633100001003003830038300383003830038
102043003722501242954725101001001000010010000500427716003001803003730037282643287451010020010000200200003003730037111020110099100100100001000007101161129633100001003003830038300383003830038
102043003722405362954725101001001000010010000500427716013001833003730037282643287451010020010000200200003003730037111020110099100100100001000017101161129633100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372320000000006129538811001010100081010000664277160030018300373003728286112893310010201000020200003017630037111002110910101000010002010006404165529629010000103003830038300383003830038
10024300372320000001501612954713410010101000010100005042771600301263003730037282863287671001020100002020000300373003711100211091010100001000000000810109681029991310000103051430549307953098130976
1002430894247202017162151160401080329457208101041510088211088261428932803023830462303172831643289351100226111472422302303683032581100211091010100001044010422198273010148101029847210000103036830370304193083530368
10024300372352000106145288006490294482131009322100962011200934308256030378305113036828328452889711514201099620200003003730037111002110910101000010420110306405165529629510000103003830038301703050930038
1002430037232210000132917607712952925100101010000101150050427716003001830037300372828632876710010221115020200003003730037111002110910101000010000000006405164629629010000103003830038300383003830038
1002430037233002094000612954725100101010000101000050427716003001830037300372828632876710010201000020200003003730037111002110910101000010000000006406166529629010000103003830038300383003830038
10024300372320000000006129547251001010100001010000504277160030018300373003728286328767100102010000202000030037300852110021109101010000100000000064012806529629010000103003830038300383003830038
10024300372250000000005362954725100101010000101000050427716003001830037300372828632876710010201000020203323003730037111002110910101000010000012606405166529629010000103008630038300863003830038
1002430037232000000000612954725100101010000101000055427716003001830037300372828632876710010201000020200003003730037111002110910101000010000000006405165529629010000103003830038300383003830038
1002430037224000000000612954725100101010000101000050427716003001830037300372828632876710010201000020200003003730037111002110910101000010000000006405165529629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  sminv h0, v8.8h
  sminv h1, v8.8h
  sminv h2, v8.8h
  sminv h3, v8.8h
  sminv h4, v8.8h
  sminv h5, v8.8h
  sminv h6, v8.8h
  sminv h7, v8.8h
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)031e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420058150003025801081008000810080020500640132200200200392003999776999080120200800322001600642003920039118020110099100100800001000011151180160020036800001002004020040200402004020040
8020420039150003025801081008000810080020500640132200200200392003999776999080120200800322001600642003920039118020110099100100800001000011151180160020036800001002004020040200402004020040
8020420039150003025801081008000810080020500640132200200200392003999776999080120200800322001600642003920039118020110099100100800001000011151180160020036800001002004020040200402004020040
8020420039150003025801081008000810080020500640132200200200392003999776999080120200800322001600642003920039118020110099100100800001000011151180160020036800001002004020040200402004020040
8020420039150003025801081008000810080020500640132200200200392003999776999080120200800322001600642003920039118020110099100100800001000011151180160020036800001002004020040200402004020040
8020420039150003025801081008000810080020500640132200200200392003999776999080120200800322001600642003920039118020110099100100800001000011151180160020036800001002004020040200402004020040
8020420039150003025801081008000810080020500640820200200200392003999776999080120200800322001600642003920039118020110099100100800001000011151180160020036800001002004020040200402004020040
8020420039150003025801081008000810080116500640132200200200392003999776999080120200800322001600642003920039118020110099100100800001000011151180160020036800001002004020040200402004020040
8020420039150003025801081008000810080020500640132200200200392003999776999080120200800322001600642003920039118020110099100100800001000011151180160020036800001002004020040200402004020088
8020420039150003025801081008000810080020500640132200200200392003999776999080120200800322001600642003920039118020110099100100800001000011151182160020036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)daddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200511500000000082258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000000050206160752003680000102004020040200402004020040
800242003915000000012040258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000000050205160572003680000102004020040200402004020040
80024200391500000000040258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000000050205160752003680000102004020040200402004020040
80024200391500000030040258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000000050205160752003680000102004020040200402004020040
800242003915000000000705258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000000050455160772003680000102004020040200402004020040
80024200391500000000040258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000009050945160772003680000102004020040200402004020040
80024200391500000000040258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000000050207160752003680000102004020040200402004020040
80024200391500000000040258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000000050207160752003680000102004020040200402004020040
80024200391500000000040258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000000050205160572003680000102004020040200402004020040
80024200391500000000040258001010800001080000506400001200202003920039999631001980010208000020160000200392003911800211091010800001000000050205160572003680000102004020040200402004020040