Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SMIN (vector, 16B)

Test 1: uops

Code:

  smin v0.16b, v0.16b, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
10042037150061168725100010001000264680120182037203715723189510001000200020372037111001100001573116111787100020382038203820382038
1004203716006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
1004203715006116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  smin v0.16b, v0.16b, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)09181e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037150000006119687251010010410012100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100570371011611197910100001002003820038200382003820087
10204200371500000061196872510100100100001001000050028476801200182003720037184223187451010020010000200200002003720037111020110099100100100001002705471011611197910100001002003820038200382003820038
102042003715000000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037150000006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100170071011611197910100001002003820038200382003820038
1020420037150000088611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715001000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
102042003715000000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010010071011611197910100001002003820038200382003820038
102042003715000000611968725101001001000010010000500284768002001820037200371842231874510100200100002002000020037200371110201100991001001000010000071011611197910100001002003820038200382003820038
1020420037150000006119687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100720371011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371500069019687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001010640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001010640216221978510000102003820038200382003820038
1002420037149008419687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010303640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010045640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680200182003720037184443187671001020101782020000200372003711100211091010100001019640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001003640216221978510000102003820038200382003820038
1002420037151006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476802001820037200371844431876710010201000020200002003720037111002110910101000010353640216221978510000102003820038200382003820038
1002420037150006119687251001010100001010000502847680200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  smin v0.16b, v1.16b, v0.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003714900761968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100097101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100037101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768020018200372003718422318745101002001018020020000200372003711102011009910010010000100067101161119791100001002003820038200382003820038
1020420037150004411968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100537101161119791100001002003820038200382003820038
1020420037150006119687251010010010000100100005002847680200182003720037184223187451010020010000200200002003720037111020110099100100100001002737101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100067101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100007101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100107101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100097101161119791100001002003820038200382003820038
102042003715000611968725101001001000010010000500284768020018200372003718422318745101002001000020020000200372003711102011009910010010000100167101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)091e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002420037150000611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
1002420037150000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
1002420037150000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
1002420037155000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
10024200371500012611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
10024200371500006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100546402162219785010000102003820038200382003820038
1002420037150000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
1002420037150000611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010006402162219785010000102003820038200382003820038
10024200371500006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100756402172219785010000102003820038200852008620038
1002420037150000611968743100231410012111015250284768012001820037200371844431876710010201000020200002003720037211002110910101000010006402162219785310000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  smin v0.16b, v8.16b, v9.16b
  smin v1.16b, v8.16b, v9.16b
  smin v2.16b, v8.16b, v9.16b
  smin v3.16b, v8.16b, v9.16b
  smin v4.16b, v8.16b, v9.16b
  smin v5.16b, v8.16b, v9.16b
  smin v6.16b, v8.16b, v9.16b
  smin v7.16b, v8.16b, v9.16b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042005615004045803031008000010080000500640000020019020038200389973399968010020080000200160000200382003811802011009910010080000100005105110327112003516800001002003920039200392003920039
80204200381500402580100100800001008000050064000002001902003820038997339996801002008000020016000020090200912180201100991001008000010020000511011611200350800001002003920039200392003920039
80204200381500402580100100800001008000050064000002001902003820038997339996801002008000020016000020038200381180201100991001008000010000000511011611200350800001002003920039200392003920039
80204200381500822580100100800001008000050064000002001902003820038997339996801002008000020016000020038200381180201100991001008000010000030511011611200350800001002003920039200392003920039
802042003815003252580100100800001008000050064000002001902003820038997339996801002008000020016000020038200381180201100991001008000010022000511011611200350800001002003920039200392003920137
80204200381500402580100100800001008000050064000002001902003820038997339996801002008000020016000020038200381180201100991001008000010000010511011611200350800001002003920039200392003920039
80204200381500402580100100800001008000050064000002001902003820038997339996801002008000020016000020038200381180201100991001008000010000000511011611200350800001002003920039200392003920039
802042003815012822580100100800001008000050064000002001902003820038997339996801002008000020016000020038200381180201100991001008000010000000511011611200350800001002003920039200392003920039
80204200381500402580100100800001008000050064000002001902003820038997339996801002008000020016000020038200381180201100991001008000010000000511011611200350800001002003920192200392003920039
8020420038150214025801001008000010080000500640000020019020038200389973399968010020080000200160000200382003811802011009910010080000100000069511011611200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd0d5map dispatch bubble (d6)ddfetch restart (de)dfe0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242004815000612580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010000502036165512003580000102003920039200392003920039
800242003815001662580010108000010800005064000002001920038200389996310018800102080000201600002003820038118002110910108000010000502033164402003580000102003920039200392003920039
8002420038150003925800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000101900502034163302003580000102003920039200392003920039
800242003815001392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010000502033163312003580000102003920039200392003920039
8002420038150006472580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010000502103163312003580000102003920039200392003920039
8002420038150014525800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000102200502033163302003580000102003920039200392003920039
800242003815000662580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010000502263165422003580000102003920039200392003920039
800242003815001392580010108000010800005064000012001920038200389996310018800102080000201600002003820038118002110910108000010000502104164412003580000102003920039200392003920039
80024200381500012325800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000102100502134164512003580000102003920039200392003920039
800242003815000117225800101080000108000050640000120019200382003899963100188001020800002016000020038200381180021109101080000102600502135164302003580000102003920039200392003920039