Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SMIN (vector, 4S)

Test 1: uops

Code:

  smin v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10042037150611687251000100010002646800201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
100420371501031687251000100010002646800201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037150911687251000100010002646800201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037150821687251000100010002646800201820372037157231895115210002000203720371110011000073116111787100020382038203820382038
10042037150821687251000100010002646800201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037150821687251000100010002646800201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037153821687251000100010002646800201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037160611687251000100010002646800201820372037157231913100010002000203720371110011000073116111787100020382038203820382038
10042037150611687251000100010002646800201820372037157231895100010002000203720371110011000073116111787100020382038203820382038
10042037150611687251000100010002646800201820372037157231895100010002000203720371110011000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  smin v0.4s, v0.4s, v1.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020420037150000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382008620038
1020420037150000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119912100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038
1020420037150000611968725101001001000010010000500284768012001820037200371842231874510100200100002002000020037200371110201100991001001000010000007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371503611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640416441978510000102003820038200382003820038
10024200371500841968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000640416341978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640416441978510000102003820038200382003820038
100242003715012611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640316431978510000102003820038200382003820038
10024200371500661968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640416341978510000102003820038200382003820038
100242003715004411968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000640416431978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000640316441978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000640316441978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768012001820037200371844431876710010201000020200002003720037111002110910101000010000640416341978510000102003820038200382003820038
10024200371500611968725100101010000101000050284768002001820037200371844431876710010201000020200002003720037111002110910101000010000640316441978510000102003820038200382003820038

Test 3: Latency 1->3

Code:

  smin v0.4s, v1.4s, v0.4s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715015611968725101001001000010010000500284768002001802003720037184223187451010020010000200200002003720037111020110099100100100001007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768002001802003720037184223187451010020010000200200002003720037111020110099100100100001007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768012001802003720037184223187451010020010000200200002003720037111020110099100100100001007101161119791100001002003820038200382003820038
102042003715015611968725101001001000010010000500284768002001802003720037184223187451010020010000200200002003720037111020110099100100100001007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768002001802003720037184223187451010020010000200200002003720037111020110099100100100001007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768012001802003720037184223187451010020010000200200002003720037111020110099100100100001007101161119791100001002003820038200382003820038
102042003715021611968725101001001000010010000500284768002001802003720037184223187451010020010168200200002003720037111020110099100100100001007101161119791100001002003820038200382003820038
10204200371509611968725101001001000010010000500284768002001802003720037184223187451010020010000200200002003720037111020110099100100100001007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768002001802003720037184223187451010020010000200200002003720037111020110099100100100001007101161119791100001002003820038200382003820038
10204200371500611968725101001001000010010000500284768002001802003720037184223187451010020010000200200002003720037111020110099100100100001007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000252196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000251196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200182018020037184443187671001020100002020000200372003711100211091010100001000640216221978510000102008620038200382003820038
10024200371500061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200371500061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
10024200841500061196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038
100242003715000726196872510010101000010100005028476801200182003720037184443187671001020100002020000200372003711100211091010100001000640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  smin v0.4s, v8.4s, v9.4s
  smin v1.4s, v8.4s, v9.4s
  smin v2.4s, v8.4s, v9.4s
  smin v3.4s, v8.4s, v9.4s
  smin v4.4s, v8.4s, v9.4s
  smin v5.4s, v8.4s, v9.4s
  smin v6.4s, v8.4s, v9.4s
  smin v7.4s, v8.4s, v9.4s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200381500004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000051104165320035800001002003920039200392003920039
80204200381500004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000051104164420035800001002003920039200392003920039
80204200381500004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000051104164420035800001002003920039200392003920039
80204200381500004025801001008000010080000500640000120019200382003899733999680205200800002001600002003820038118020110099100100800001000051104164520035800001002003920039200392003920039
80204200381500004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000051105164520035800001002003920039200392003920039
80204200381500004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000051105165420035800001002003920039200392003920039
80204200381500004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000051103163520035800001002003920039200392003920039
80204200381500004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000051104164520035800001002003920039200392003920039
80204200381500304025801001008000010080000500640000120019200382003899738999680100200800002001600002003820038118020110099100100800001000051104164520035800001002003920039200392003920039
80204200381500004025801001008000010080000500640000120019200382003899733999680100200800002001600002003820038118020110099100100800001000051104165420035800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fst unit uop (a7)l1d cache writeback (a8)a9accfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200481500103039258001010800001080000506400005102001920038200389996310018800102080000201600002003820038118002110910108000010000350200071671020035080000102003920039200392003920039
80024200381500109812580010108000010800005064000051020019200382003899963100188001020800002016000020038200381180021109101080000100100502000101610820035080000102003920039200392003920039
8002420038150010022925800101080000108000050640000510200192003820038999631001880010208000020160000200382003811800211091010800001011435020001016101020035080000102003920039200392003920039
8002420038155010981258001010800001080000506400005152005820038200389996310018800102080000201600002003820038118002110910108000010000050200071671020035080000102003920039200392003920039
800242003815001318392580010108000010800005064000051020019200382003899963100188001020800002016000020038200381180021109101080000100000502000101681020035080000102003920039200392003920039
8002420038150010123925800101080000108000050640000510200192003820038999631001880010208000020160000200382003811800211091010800001000005020001016101020035080000102003920039200392003920039
80024200381500100392580010108000010800005064000041020019200382003899963100188001020800002016000020038200381180021109101080000100000502000101610720035080000102003920039200392003920039
80024200381490100392580103108000010800005064000041520019200382003899963100188001020800002016000020038200381180021109101080000100109502000101671020035080000102003920039200392003920039
80024200381500100392580010108000010800005064000041020019200382003899963100188001020800002016000020038200381180021109101080000100000502000101671020035080000102003920039200392003920039
80024200381500100392580010108000010800005064000041020019200382003899963100188001020800002016000020038200381180021109101080000100000502000101671020035080000102003920039200392003920039