Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SMIN (vector, 8H)

Test 1: uops

Code:

  smin v0.8h, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371508216872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371506116872510001000100026468012018203720371572318951000100020002037203711100110000073116111787100020382038203820382038
100420371538416872510001000100026468002018203720371572318951000100020002037203711100110000073116111787100020382038203820382038

Test 2: Latency 1->2

Code:

  smin v0.8h, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
1020420037150000189196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
1020420037150000488196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
102042003715000061196872510100100100001001000050028476802001820037200841842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
1020420037150100126196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038
1020420037150000568196872510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010017101161119791100001002003820038200382003820038
102042003715000061196672510100100100001001000050028476802001820037200371842231874510100200100002002000020037200371110201100991001001000010007101161119791100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)0309l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100242003715000000022119687251001010100001010000502847680020018200372003718444318787100102010000202000020037200371110021109101010000100000000006402162219785010000102003820038200382003820038
10024200371500000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000000006402162219785010000102003820038200382003820038
10024200371500000006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000000006402162219785010000102003820038200382003820038
100242003715000000048219687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000023993006402162219785010000102003820038200382003820038
100242008515000000012619687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100000000006402162219785010000102003820038200382003820038
100242003715000006606119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000000006402162219785010000102003820038200382003820038
100242003715000000033419687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000000006402162219785010000102003820038200382003820038
100242003715000000019119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000000006402162219785010000102003820038200382003820038
10024200371500000006119687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000003006402162219785010000102003820038200382003820038
100242003715000000010319687251001010100001010000502847680120018200372003718444318767100102010000202000020037200371110021109101010000100000000006402162219785010000102003820038200382003820038

Test 3: Latency 1->3

Code:

  smin v0.8h, v1.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
1020420037150061196872510100100100001001000050028476800200182003720037184223187451010020010000200200002003720037111020110099100100100001000710116111979119100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
102042003715008419687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
1020420037150010719687251010010010000100100005002847680120018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038
102042003715006119687251010010010000100100005002847680020018200372003718422318745101002001000020020000200372003711102011009910010010000100071011611197910100001002003820038200382003820038

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024200371506936119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100640316221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000662847680020018200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
10024200371503336119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
1002420037150053619687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038
100242003715006119687251001010100001010000502847680020018200372003718444318767100102010000202000020037200371110021109101010000100640216221978510000102003820038200382003820038

Test 4: throughput

Count: 8

Code:

  smin v0.8h, v8.8h, v9.8h
  smin v1.8h, v8.8h, v9.8h
  smin v2.8h, v8.8h, v9.8h
  smin v3.8h, v8.8h, v9.8h
  smin v4.8h, v8.8h, v9.8h
  smin v5.8h, v8.8h, v9.8h
  smin v6.8h, v8.8h, v9.8h
  smin v7.8h, v8.8h, v9.8h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042006015000600402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000511021611200350800001002003920039200392003920039
802042003815000600402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000511011611200350800001002009020039200392003920039
8020420038150002700402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000511011611200350800001002003920039200392003920039
8020420038150005100402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000511011611200350800001002003920039200392003920039
8020420038150003300402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000511011611200350800001002003920039200392003920039
8020420038150000003252580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000511011611200350800001002003920039200392003920039
80204200381500028500402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000511011651200350800001002003920039200392003920039
802042003815000000402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000511011611200350800001002003920039200392003920039
802042003815000000402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000511011611200350800001002003920039200392003920039
8020420038150001800402580100100800001008000050064000020019200382003899733999680100200800002001600002003820038118020110099100100800001000000511011611200350800001002003920039200392003920039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420048150000000039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000000000050206162420035080000102003920039200392003920039
8002420038150000000039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000000000050204164420035080000102003920039200392003920039
80024200381500000000520258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000000000050203162420035080000102003920039200392003920039
8002420038150000000039258001010800001180000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000000000050204162420035080000102003920039200392003920039
8002420038150000000039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000000060050202164220035080000102003920039200392003920039
8002420038150000000039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000000000050202162420035080000102003920039200392003920039
8002420038150000000039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000000000050204164220035080000102003920039200392003920039
8002420038150000000039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000000000050204164220035080000102003920039200392003920039
8002420038150000000039258001010800001080000506400000200192003820038999631001880010208000020160000200382003811800211091010800001000000000150204164420035080000102003920039200392003920039
8002420038150000000039258001010800001080000506400001200192003820038999631001880010208000020160000200382003811800211091010800001000000000050202164220035080000102003920039200392003920039