Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SMLAL2 (vector, 4S)

Test 1: uops

Code:

  smlal2 v0.4s, v1.8h, v2.8h
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372306125482510001000100039831303018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
1004303722346725482510001000100039831303018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
10043037231896125482510001000100039831303018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
10043037231596125482510001000100039831313018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831303018303730372415328951000100030003037303721100110000073116112630100030383038303830383038
100430372306125482510001000100039831303018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831303018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372308225482510001000100039831303018303730372415328951000100030003037303711100110000373116112630100030383038303830383038
100430372306125482510001000100039831303018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831303018303730372415328951000100030003037303711100110000073116112630100030383038303830383038

Test 2: Latency 1->1

Code:

  smlal2 v0.4s, v1.8h, v2.8h
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500168295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000071002162229634100001003003830038300383003830038
102043003722500189295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000210071002162229634100001003003830038300383003830038
102043003722500149295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000000071002162329634100001003003830038300383003830038
1020430037225004727295482510100100100001001000050042773130300183003730037282653287451010020010000202300003003730037111020110099100100100001000000071012162229634100001003003830038300383003830038
102043003722500210295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000071012162229634100001003003830038300383003830038
102043003722400191295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000071012162229634100001003003830038300383003830038
102043003722400166295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000000071012162229634100001003003830038300383003830038
102043003722500214295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000071012162229634100001003003830038300383003830038
102043003722400191295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000071013162329634100001003003830038300383003830038
102043003722400124295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000071012162229634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)a9acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722501452954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010002280506403162229630010000103003830038300383003830038
100243003722509642954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000006402162229630010000103003830038300383003830038
100243003722502142954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000006403164329741010000103003830038300383003830038
100243003722501702954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000006402163329630110000103003830038300383003830038
100243003722501912954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000006402162329630010000103003830038300383003830038
100243003722501032954825100101010000101000050427731323001830037300372828732876710010201000020300003003730037111002110910101000010000006402162229630010000103003830038300383003830038
100243003722502142954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000006402162229630010000103003830038300383003830038
100243003722501892954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000006403162229630010000103003830038300383003830038
100243003722501262954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000006402162229630010000103003830038300383003830038
100243003722501492954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000006402162229630010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  smlal2 v0.4s, v0.8h, v1.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)0918191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250000000612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000000071031622297060100001003003830038300383003830038
10204300372250000000822954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000000071021622297020100001003003830038300383003830038
10204300372250000000612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000000071021622296340100001003003830038300383003830038
1020430037225000000021012954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000120071021622296340100001003003830038300383003830038
102043003722500000001892954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000000071021622296340100001003003830038300383003830038
102043003722500000001682954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000000071021622296340100001003003830038300383003830038
102043003722500000004412954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000003071021622296340100001003003830038300383003830038
102043003722500000004602954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000000071021622296340100001003003830038300383003830038
10204300372250000426004512954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000000071021622296340100001003003830038300383003830038
102043003722500100002332954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000100071021622296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000000503329548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243003722500000034629548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
10024300372250000006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243003722500000017029548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000640216212963010000103003830038300383003830038
100243003722500000012429548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243003722400000046229548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243003722500000063129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300821110021109101010000100000640216222963010000103003830038300383003830038
100243003722500000063129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038

Test 4: Latency 1->3

Code:

  smlal2 v0.4s, v1.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fa9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372242461295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
10204300372250726295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
10204300372250346295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
10204300372240251295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
10204300372250171295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
10204300372250536295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000371011611296340100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
10204300372250726295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
10204300372250251295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000071011611296340100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000640416342963010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000640416342963010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000640316342963010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000640316342963010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000640316342963010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000640416342963010000103003830038300383003830038
1002430037224000822954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000640416342963010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000640416442963010000103013230084300383003830038
1002430037225000612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010030640416432963010000103003830038300383003830038
1002430037225000612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000640316342963010000103003830038300383003830038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  smlal2 v0.4s, v8.8h, v9.8h
  movi v1.16b, 0
  smlal2 v1.4s, v8.8h, v9.8h
  movi v2.16b, 0
  smlal2 v2.4s, v8.8h, v9.8h
  movi v3.16b, 0
  smlal2 v3.4s, v8.8h, v9.8h
  movi v4.16b, 0
  smlal2 v4.4s, v8.8h, v9.8h
  movi v5.16b, 0
  smlal2 v5.4s, v8.8h, v9.8h
  movi v6.16b, 0
  smlal2 v6.4s, v8.8h, v9.8h
  movi v7.16b, 0
  smlal2 v7.4s, v8.8h, v9.8h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602042009015002925801161008001610080028500640196200452006520065612801282008002820024008420065200651116020110099100100160000100000011110119416002006201600001002006620066200662006620066
1602042006515002925801161008001610080028500640196200452006520065612801282008002820024008420065200651116020110099100100160000100000011110119016002006201600001002006620066200662006620066
16020420065150019425801001008000010080000500640000200452006420064322801002008000020024000020064200641116020110099100100160000100000000010111116112006101600001002006520065200652006520065
160204200641514563925801001008000010080000500640000200452006420064322801002008000020024000020064200641116020110099100100160000100000000010111116112006101600001002006520065200652006520065
16020420064150513925801001008000010080000500640000200452006420064322801002008000020024000020064200641116020110099100100160000100000000010111116112006101600001002006520065200652006520065
1602042006415003925801001008000010080000500640000200452006420064322801002008000020024000020064200641116020110099100100160000100000000010111116112006101600001002006520065200652006520065
1602042006415003925801001008000010080000500640000200452006420064322801002008000020024000020064200641116020110099100100160000100000000010111116112006101600001002006520065200652006520065
1602042006415003925801001008000010080000500640000200452006420064322801002008000020024000020064200641116020110099100100160000100000900010111249112006151600001002006520065200652006520065
1602042006415003925801001008000010080000500640000200452006420064322801002008000020024000020064200641116020110099100100160000100000000010111116112006101600001002006520065200652006520065
1602042006415003925801001008000010080000500640000200452006420064322801002008000020024000020064200641116020110099100100160000100000000010111116112006101600001002006520065200652006520065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03l2 tlb miss data (0b)191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600242006415000045258001212800001280000626400001120027200462004632280012208000020240000200462004611160021109101016000010000000100313115202115620043215160000102004720047200472004720047
1600242004615000045258001212800001280000626400000120027200462004632280012208000020240000200462004611160021109101016000010000000100313128202118820043230160000102004720047200472004720047
1600242004615000045258001212800001280000626400001120027200462004632280012208000020240000200462004611160021109101016000010000000100313117202118820043215160000102004720047200472004720047
1600242004615000045258001212800001280000626400001120027200462004632280012208000020240000200462004611160021109101016000010000000100293117202116520047215160000102005320047200472005120047
1600242004615000045258001212800001280000626400001120027200462004632280012208000020240000200502004611160021109101016000010000030100313117202116820043215160000102004720047200472004720047
1600242004615000045258001212800001280000626400001120027200462004632280012208000020240000200462004611160021109101016000010000000100333126202117720043215160000102004720047200472004720047
1600242004615000087258001212800001280000626400001120027200462004632280012208000020240000200462004611160021109101016000010000004100313115202116820043215160000102004720047200472004720047
1600242005215000045258001212800001280000626400001120027200462005032280012208000020240000200462004611160021109101016000010000000100323125202216520043215160000102004720047200472004720047
16002420046150000710258001212800001280000626400001120027200462004632280012208000020240000200462004611160021109101016000010000000100303115202118520051215160000102004720051200472004720047
16002420046150002145258001212800001280000626400000120033200462004632280012208000020240000200462004611160021109101016000010000000100296118202115520043215160000102004720047200472004720047

Test 6: throughput

Count: 16

Code:

  smlal2 v0.4s, v16.8h, v17.8h
  smlal2 v1.4s, v16.8h, v17.8h
  smlal2 v2.4s, v16.8h, v17.8h
  smlal2 v3.4s, v16.8h, v17.8h
  smlal2 v4.4s, v16.8h, v17.8h
  smlal2 v5.4s, v16.8h, v17.8h
  smlal2 v6.4s, v16.8h, v17.8h
  smlal2 v7.4s, v16.8h, v17.8h
  smlal2 v8.4s, v16.8h, v17.8h
  smlal2 v9.4s, v16.8h, v17.8h
  smlal2 v10.4s, v16.8h, v17.8h
  smlal2 v11.4s, v16.8h, v17.8h
  smlal2 v12.4s, v16.8h, v17.8h
  smlal2 v13.4s, v16.8h, v17.8h
  smlal2 v14.4s, v16.8h, v17.8h
  smlal2 v15.4s, v16.8h, v17.8h
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03191e373f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
16020440049300024004125160100100160000100160000500239899914002940039400481997331999716010020016000020048000040049400391116020110099100100160000100001011011611400361600001004004040041400404004040040
160204400393000005025160100100160000100160000500128000004002040039400481997331999816010020016000020048000040040400391116020110099100100160000100001011011611400361600001004004940040400504004040049
160204400392990840174225160100100160000100160000500239899914002040048400391997331999716010020016000020048000040040400391116020110099100100160000100001011011611400361600001004004040040400404004040040
160204400403000014225160117100160000100160000500239899914002140040400391997332000716010020016000020048000040039400481116020110099100100160000100001011011611400361600001004004040041400404005040049
16020440039300001770625160117100160017100160000500128000004002140039400391997332002416010020016000020048000040039400481116020110099100100160000100001011011611400371600001004004040041400404004140040
160204400392990014125160101100160000100160000500131999804002040048400391997331999716010020016000020048000040039400481116020110099100100160000100001011011611400461600001004004040049400404004940040
160204400403000624175025160100100160000100160000500128000004002940040400391997331999816010020016000020048000040039400391116020110099100100160000100001011011633400371600001004004040049400414004040041
1602044003930009175025160100100160000122160000500131999804002040039400391997331999716010020016000020048000040040400391116020110099100100160000100001011011611400371600001004004940040400404004940040
160204400393000004125160100100160000100160000500131999814003040039400391997331999816010020016000020048000040039400481116020110099100100160000100001011011611400361600001004004140040400504005040040
160204400393000004225160117100160001100160000500128000004003040049400491998431999716010020016000020048000040039400481116020110099100100160000100001011011611400361600001004004140090400524004040040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)031e373f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600244005230000562516001010160018101600005012800001040020400484003919996320019160010201600002048000040039400391116002110910101600001000100223111216211141140045206160000104004040040400404004040040
1600244004929900130251600281016000010160000502438865114002040039400391999632001916001020160000204800004003940039111600211091010160000100010022311101621181040036206160000104004040040400404004040040
160024400393000185625160010101600011016000050128000010400204004040039199963200191600102016000020480000400394003911160021109101016000010001002231171621110740036207160000104004040040400404004040040
1600244003930000711251600101016000010160000501280000114002040039400391999692002916001020160000204800004003940039111600211091010160000100010022311101621113840036206160000104004040040400404004040050
16002440039300807146251600101016000010160000501280000104002040039400391999632002916001020160000204800004003940039111600211091010160000100010022311101621110740036207160000104004040040400404004040040
16002440039300540046251600281016000010160000501280000104002040039400391999632001916001020160000204800004003940039111600211091010160000100010022311131621110740046206160000104004140040400404004040040
160024400392996750462516001010160000101600005012800001140020400394003919996320029160010201600002048000040039400391116002110910101600001000100223111116211101040036206160000104004040040400404004040040
1600244004930000436251600281016000010160000501280000114002040039400391999632002916001020160000204800004003940039111600211091010160000100010022311816211111240036206160000104004040040400404004040040
160024400392990056251600101016000010160000501280000114002040039400391999632001916001020160000204800004003940039111600211091010160000100010022311101621112840036206160000104004040040400404004040040
16002440049299513046251600101016000010160000502438865114003040049400391999632002916001020160000204800004003940039111600211091010160000100010022311121621181040036206160000104004040049400404004040041