Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SMLAL (vector, 2D)

Test 1: uops

Code:

  smlal v0.2d, v1.2s, v2.2s
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303722016125482510001000100039831313018303730372415328951000100030003037303711100110003075616662630100030383038303830383038
1004303723016125482510001000100039831313018303730372415328951000100030003037303711100110001075516552630100030383038303830383038
10043037220125125482510001000100039831313018303730372415328951000100030003037303711100110000075516662630100030383038303830383038
1004303723016125482510001000100039831303018303730372415328951000100030003037303711100110000075516552630100030383038303830383038
1004303723016125482510001000100039831303018303730372415328951000100030003037303711100110000075516662630100030383038303830383038
1004303723026125482510001000100039831303018303730372415328951000100030003037303711100110000075516662630100030383038303830383038
1004303723016125482510001000100039831303018303730372415328951000100030003037303711100110000075616662630100030383038303830383038
1004303723016125482510001000100039831303018303730372415328951000100030003037303711100110000075516562630100030383038303830383038
1004303723016125482510001000100039831303018303730372415328951000100030003037303711100110000075616662630100030383038303830383038
1004303723016125482510001000100039831303018303730372415328951000100030003037303711100110000075516662630100030383038303830383038

Test 2: Latency 1->1

Code:

  smlal v0.2d, v1.2s, v2.2s
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250000000287295482510124100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000710131622296340100001003003830038300383003830038
1020430037225000000061295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000710121623296340100001003003830038300383003830038
1020430037225000000061295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000710121622296340100001003003830038300383003830038
1020430037225000000061295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000710121622296340100001003003830038300383003830038
1020430037225000000061295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000710121622296340100001003003830038300383003830038
10204300372250000000726295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000710121622296340100001003003830038300383003830038
1020430037224020000061295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000710121622296340100001003003830038300383003830038
1020430037225000000061295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000710121622296340100001003003830038300383003830038
1020430037225000000061295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000710121622296340100001003003830038300383003830038
1020430037225000000061295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000710121622296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e5051schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250612954802510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372250612954802510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372240612954802510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372250612954802510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103013230085301333013330038
10024300372250612954802510010101000010100005042773130300183003730037282923287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372250612954802510010101000010100005042773130300183003730037282873287671001020100002030510300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372250612954802510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372250612954802510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372240612954802510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000640216222963010000103003830038300383003830038
10024300372250612953902510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001030640216222963010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  smlal v0.2d, v0.2s, v1.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225046829548251010010010000100100005004277313300183003730037282653287451010020010000200300003003730037111020110099100100100001000000007102162229706100001003003830038300383003830038
10204300372250126029548251010010010000100100005004277313300183003730037282653287451010020010000200300003003730084111020110099100100100001000000007102162229634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313300183003730037282653287451010020010000200300003003730037111020110099100100100001005200007102162229634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313300183003730037282653287451010020010000200300003003730037111020110099100100100001000000007102162229634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313300183003730037282653287451010020010000200300003003730037111020110099100100100001000000007102162229634100001003003830038300383003830038
102043003722406129548251010010010000100100005004277313300183003730037282653287451010020010000200300003003730037111020110099100100100001000000007102162229634100001003003830038300383003830038
1020430037225088129548251010010010000100100005004277313300183003730037282653287451010020010000200300003003730037111020110099100100100001000000007102162229634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313300183003730037282653287451010020010000200300003003730037111020110099100100100001000000007102162229634100001003003830038300383003830038
1020430037225034229548251010010010000100100005004277313300183003730037282653287451010020010000200300003003730037111020110099100100100001000000007102162229634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313300183003730037282653287451010020010000200300003003730037111020110099100100100001000000007102162229634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372240000612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000000006406162229630010000103003830038300383003830038
10024300372250000612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000000306402162229630010000103003830038300383003830038
10024300372250000612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
10024300372240000612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
10024300372250000822954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
10024300372250000612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
10024300372250000612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
10024300372250000612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
10024300372250000612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000000006402162229630010000103003830038300383003830038
10024300372250000612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000000006402162229630010000103003830038300383003830038

Test 4: Latency 1->3

Code:

  smlal v0.2d, v1.2s, v0.2s
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722501052954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722502542954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722502142954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102053003722507682954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722508522954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000027101161129634100001003003830038300383003830038
102043003722501892954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722501492954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722501912954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722408332954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
1020430037224578332954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000007571161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225001452954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
1002430037225005552954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
1002430037225001262954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
1002430037225001032954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731330018300373008428287328767100102010000203000030037300371110021109101010000100400640216222963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
1002430037225001702954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
1002430037225001452954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100001640216222963010000103003830038300383003830038
1002430037225001032954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038
1002430037225001912954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100000640216222963010000103003830038300383003830038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  smlal v0.2d, v8.2s, v9.2s
  movi v1.16b, 0
  smlal v1.2d, v8.2s, v9.2s
  movi v2.16b, 0
  smlal v2.2d, v8.2s, v9.2s
  movi v3.16b, 0
  smlal v3.2d, v8.2s, v9.2s
  movi v4.16b, 0
  smlal v4.2d, v8.2s, v9.2s
  movi v5.16b, 0
  smlal v5.2d, v8.2s, v9.2s
  movi v6.16b, 0
  smlal v6.2d, v8.2s, v9.2s
  movi v7.16b, 0
  smlal v7.2d, v8.2s, v9.2s
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9facbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
16020420090150039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100001011221622200611600001002006520065200652006520065
16020420064150039258010010080000100800006086400000200452006420064322801002008000020024000020064200641116020110099100100160000100001011221622200611600001002006520065200652006520065
16020420064151039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100001011221622200611600001002006520065200652006520065
16020420064150065258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100001011221622200611600001002006520065200652006520065
160204200641501539258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100001011221622200611600001002006520065200652006520065
16020420064150039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100001011221622200611600001002006520065200652006520065
16020420064150039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100001011221622200611600001002006520065200652006520065
16020420064150039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100001011221622200611600001002006520065200652006520065
160204200641511239258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100001011221622200611600001002006520065200652006520065
16020420064151039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100001011221622200611600001002006520065200652006520065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696b6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaec? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600242008815000000000135258001212800001280000626400001152002702005020050322800122080000202400002004620046111600211091010160000100000001003281219204111919200432150160000102014920047200512004720051
16002420046151000000004525800121280000128000062640000015200270200462004632280012208000020240000200502004611160021109101016000010000000100428411820412919200432150160000102004720047200472004720051
16002420046150000000008925800121280000128000062640000115200270200462004632280012208000020240000200462005011160021109101016000010000000100428411820421188200432150160000102004720051200472004720051
160024200501500000000013125800121280000128000062640000015200310200462005032280012208000020240000200462004611160021109101016000010000000100458411820212919200472150160000102004720047200472004720047
160024200501500000000011025800121280000128000062640000115200270200462004632280012208000020240000200462004611160021109101016000010000000100458511820411718200432150160000102004720047200512004720051
1600242004615000000000452580012128031412800006264000011520027020046200463228001220800002024000020121200751116002110910101600001000000010042841620211718200432150160000102005120047200472005120047
16002420046150000000004525800121280000128000062640000115200313200462004632280012208000020240000200462005011160021109101016000010000000100308428202131197200432150160000102005120047200512004720047
1600242004615000000000116258001212800001280000626400000152002702004620046322800122080000202400002005020050111600211091010160000100000001004211511820212197200432150160000102004720047200472004720047
16002420046150000000004525800121280000128000062640000115200270200462005032280012208000020240000200462004611160021109101016000010000000100428411820212819200432150160000102004720047200512005120047
1600242004615000000000452580012128000012800006264000011520027020046200463228001220800002024000020046200461116002110910101600001000000010042851820211718200432150160000102005120047200472004720047

Test 6: throughput

Count: 16

Code:

  smlal v0.2d, v16.2s, v17.2s
  smlal v1.2d, v16.2s, v17.2s
  smlal v2.2d, v16.2s, v17.2s
  smlal v3.2d, v16.2s, v17.2s
  smlal v4.2d, v16.2s, v17.2s
  smlal v5.2d, v16.2s, v17.2s
  smlal v6.2d, v16.2s, v17.2s
  smlal v7.2d, v16.2s, v17.2s
  smlal v8.2d, v16.2s, v17.2s
  smlal v9.2d, v16.2s, v17.2s
  smlal v10.2d, v16.2s, v17.2s
  smlal v11.2d, v16.2s, v17.2s
  smlal v12.2d, v16.2s, v17.2s
  smlal v13.2d, v16.2s, v17.2s
  smlal v14.2d, v16.2s, v17.2s
  smlal v15.2d, v16.2s, v17.2s
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)0318191e1f373f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602044004830000001841251601001001600001001600005002398999400294004840040199730319997160100200160000200480000400394004911160201100991001001600001000000010110116114003601600001004004040049400404004940040
1602044003930000001741251601171001600171001600005001280000400204003940040199730320007160100200160000200480000400394004811160201100991001001600001000000010110116114003601600001004004940050400414004940049
1602044004830000000412516010010016000010016000050012800004002040039400391997303199981601002001600002004800004003940039111602011009910010016000010000000101101161140036231600001004004040040400494004940040
1602044003929900001741251601001001600011001600005002398999400204003940039199730319997160100200160000200480000400394004811160201100991001001600001000000010110116114003601600001004004040049400494004040049
160204400402990000074251601001001600001181600005002398999400204003940039199730319997160100200160000200480000400394003921160201100991001001600001000000110110116114004501600001004004040049400404004040040
16020440048300000017715251601171001600001001600005001280000400204003940048199730319997160100200160000200480000400494004811160201100991001001600001000000010110116114003601600001004004040049400404004940040
1602044004830000001750251601001001600001001600005002398999400204004840039199730319997160100200160000200480000400494004811160201100991001001600001000000010110116114004501600001004004940040400494004040049
160204400483000000041251601171001600001001600005001280000400204004840048199737319997160100200160000200480000400484003911160201100991001001600001000000010127116114003601600001004004140040400414004040052
1602044004029900001741251601171001600011001600005002398999400294004040048199730320006160100200160000200480000400404003911160201100991001001600001000000010110216114004501600001004004940040400404004040049
160204400482990000142251601171001600171001600005002398999400204004840039199730320006160100200160000200480000400484003911160201100991001001600001000000010110116114003601600001004007440040400404005040040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)191e1f373f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024400483000000004625160010101600001016000050128000011400204003940039199963200201600102016000020480000400394003911160021109101016000010000100223114162113440036155160000104004040040400404004040040
1600244003930000000080625160010101600001016000050128000011400294004840039199963200191600102016000020480000400394003911160021109101016000010000100223114162113440036155160000104004040049400404004940049
16002440039300000013204625160027101600001016000050128000011400294003940039199963200191600102016000020480000400394003911160021109101016000010003100223113162113440036305160000104004940040400404004940040
160024400393000000004625160010101600001016000050128000011400204003940039199963200191600102016000020480000400394003911160021109101016000010000100223113162113440036155160000104004040040400404004040040
1600244004829900000175525160010101600001016000050128000011400204003940039199963200191600102016000020480000400394003911160021109101016000010000100223113162113440045155160000104004040040400404004940040
160024400483000000004625160027101600001016000050239899911400294003940039199963200191600102016000020480000400484003911160021109101016000010000100223113162113940045155160000104004040040400404004040040
160024400483000000004625160010101600001016000050128000011400204003940039199963200191600102016000020480000400484003911160021109101016000010000100223124162114340036155160000104004040040400494004040049
160024400483001000006125160010101600001016000050128000011400294003940039199963200191600102016000020480000400394003911160021109101016000010000100223114162123440036155160000104004040040400404004040040
1600244003930000000046251600101016000010160000501280000114002040039400391999632001916001020160000204800004003940039111600211091010160000100001002231110162114340036155160000104004940040400404004040040
1600244003930000000174625160010101600171016000050128000011400204003940048199963200281600102016000020480000400394004811160021109101016000010000100223114162114340036305160000104004040040400404004040040