Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SMLAL (vector, 4S)

Test 1: uops

Code:

  smlal v0.4s, v1.4h, v2.4h
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303723010525482510001000100039831303018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
1004303723126125482510001000100039831313018303730372415328951000100030003037303711100110001073116112630100030383038303830383038
100430372206125482510001000100039831303018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
1004303723126125482510001000100039831303018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372208225482510001000100039831303018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831303018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831303018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831303018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372208225482510001000100039831303018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372308225482510001000100039831313018303730372415328951000100030003037303711100110000073116112630100030383038303830383038

Test 2: Latency 1->1

Code:

  smlal v0.4s, v1.4h, v2.4h
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430084225006129548251010010010000100100005004277313030018030037300372826532874510100200100002003000030037300371110201100991001001000010000710031622296340100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313130018330037300372826532874510100200100002003000030037300371110201100991001001000010000710121622296340100001003003830038300383003830038
1020430037224006129548251010010010000100100005004277313030018030037300372826532874510100200100002003000030037300371110201100991001001000010000712121622296340100001003003830038300383003830038
10204300372250082029548251010010010000100100005004277313130018030037300372826532874510100200100002003000030037300371110201100991001001000010000710121622296340100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313030018030037300372826532874510100200100002003000030037300371110201100991001001000010000710121622296340100001003003830038300383003830038
10204300372250075529548251010010010000100100005004277313030018030037300372826532874510100200100002003000030037300371110201100991001001000010000710121622296340100001003003830038300383003830038
1020430037224006129548251010010010000100100005004277313130018030037300372826532874510100200100002003000030037300371110201100991001001000010000710121622296340100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313030018030037300372826532874510100200100002003000030037300371110201100991001001000010000710121632296340100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313030018030037300372826532874510100200100002003000030037300371110201100991001001000010000710121622296340100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313030018030037300372826532874510100200100002003000030037300371110201100991001001000010000710121623296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000000000612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000000006403162329630010000103003830038300383003830038
1002430037224000000000612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000000006402162329630010000103003830038300383003830038
1002430037225000000000612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000000006403163329630010000103003830038300383003830038
1002430037225000000000612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000000006403162229630010000103003830038300383003830038
1002430037225000000000612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000000006403163329630010000103003830038300383003830038
1002430037225000000000612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000000006842162329630010000103003830038300383003830038
1002430037225000000000612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000000006403163329630010000103003830038300383003830038
1002430037225000000000612954825100101010000101000050427731313001830037300372828732876710010201000020300003003730037111002110910101000010000000006403164229630010000103003830038300383003830038
1002430037225000000600612954825100101010000101000050427731303001830037300372828732876710010201000020305163003730037111002110910101000010000000006402162329630010000103003830038300383003830038
1002430037225000000000612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000000006402163229630010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  smlal v0.4s, v0.4h, v1.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0318191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500726129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100007102161129634100001003003830038300383003830038
1020430037225001926129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
102043003722500696129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430084225002616129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373008411102011009910010010000100007101161129634100001003003830038300383003830038
102043003722500336129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225003666129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
10204300372250006129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225003306129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830038300383003830038
1020430037225003516129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100007101161129634100001003003830085300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225492612954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100006404164429630010000103003830038300383003830038
1002430037225144612954825100191010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100006403163429630010000103003830038300383003830038
1002430037225498612954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100006404164329630010000103003830038300383003830038
1002430037225501892954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100006404164429630010000103003830038300383003830038
1002430037225492612954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100006404164429630010000103003830038300383003830038
1002430037225732612954825100101010000101000050427731330018300373003728287328767101622010000203000030037300371110021109101010000100006404163429630010000103003830038300383003830038
10024300372250612954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100006403164329630010000103003830038300383003830038
1002430037224435612954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100006403164429630010000103003830038300383003830038
10024300372250612954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100006404164429630010000103003830038300383003830038
10024300372259612954825100101010000101000050427731330018300373003728287328767100102010000203000030037300371110021109101010000100006404164329630010000103003830038300383003830038

Test 4: Latency 1->3

Code:

  smlal v0.4s, v1.4h, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0318191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003726000061295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003726000061295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003724100061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730070111020110099100100100001002007101161129634100001003003830038300383003830038
102043003724200061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003008730038300383003830038
102043003724100061295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003724100061295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001001007101161129634100001003003830038300383003830038
102043003723300361295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000307101161129634100001003003830038300383003830038
10204300372330012271295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722900061295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003723000061295482510100100100001001000050042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0318191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500061295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000640416332963010000103003830038300383003830038
100243003722500061295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000640316332963010000103003830038300383003830038
100243003722400061295302510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000640316332963010000103003830038300383003830038
100243003722503061295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000640316332963010000103003830038300383003830038
100243003722500061295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000640316332963010000103003830038300383003830038
1002430037225000536295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000640316332963010000103003830038300383003830038
100243003722500061295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000640316332969810000103003830038300383003830038
100243003722500061295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000640316332963010000103003830038300383003830038
100243003722400061295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000640316332963010000103003830038300383003830038
100243003722500061295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000640316332963010000103003830038300383003830038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  smlal v0.4s, v8.4h, v9.4h
  movi v1.16b, 0
  smlal v1.4s, v8.4h, v9.4h
  movi v2.16b, 0
  smlal v2.4s, v8.4h, v9.4h
  movi v3.16b, 0
  smlal v3.4s, v8.4h, v9.4h
  movi v4.16b, 0
  smlal v4.4s, v8.4h, v9.4h
  movi v5.16b, 0
  smlal v5.4s, v8.4h, v9.4h
  movi v6.16b, 0
  smlal v6.4s, v8.4h, v9.4h
  movi v7.16b, 0
  smlal v7.4s, v8.4h, v9.4h
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602042006515102925801161008001610080028500640196020045200652006561280128200800282002400842006520065111602011009910010016000010000611110119416002006201600001002006620066200662006620066
1602042006515002925801161008001610080028500640196020045200652014861280128200800282002400842006520065111602011009910010016000010000311110119016002006201600001002006620066200662006620066
1602042006515003925801001008000010080000500640000020045200642006432280100200800002002400002006420064111602011009910010016000010000300010111116112006101600001002006520065200652006520065
1602042006415003925801001008000010080000500640000020045200642006432280100200800002002400002006420064111602011009910010016000010000000010111116112006101600001002006520065200652006520065
1602042006415003925801001008000010080000500640000020045200642006432280100200800002002400002006420064111602011009910010016000010000000010111116112006101600001002006520065200652006520065
1602042006415003925801001008000010080000500640000020045200642006432280100200800002002400002006420064111602011009910010016000010000000010111116112006101600001002006520065200652006520065
1602042006415003925801001008000010080000500640000020045200642006432280100200800002002400002006420064111602011009910010016000010000300010111116112006101600001002006520065200652006520065
16020420064150039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100002400010111116112006101600001002006520065200652006520065
1602042006415003925801001008000010080000500640000020045200642006432280100200800002002400002006420064111602011009910010016000010000000010111116112006101600001002006520065200652006520065
16020420064150039258010010080000100800005006400000200452006420064322801002008000020024000020064200641116020110099100100160000100007200010111116112006101600001002006520065200652006520065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk data (08)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024200631501000004525800121280000128000062640000112002720046200463228001220800002024000020046200461116002110910101600001000000100283116202115620043215160000102004720047200472004720047
160024200461501000004525800121280000128000062640000112002720046200463228001220800002024000020046200461116002110910101600001000000100293116202116520043215160000102004720047200472004720047
160024200461500000004525800121280000128000062640000112002720046200463228001220800002024000020046200461116002110910101600001000100100303117202117520043215160000102004720047200472004720047
160024200461500000004525800121280000128000062640000112002720046200463228001220800002024000020046200461116002110910101600001000000100293117202115620043215160000102004720047200472004720047
160024200461510000004525800121280000128000062640000112002720046200463228001220800002024000020046200461116002110910101600001000000100296115202115620043215160000102004720047200472004720047
160024200461500000005125800121280105128000062640000112002720046200463228001220800002024000020046200501116002110910101600001000000100303118202115720043215160000102004720047200472004720051
160024200461500000004525800121280000128000062640000112002720046200463228001220800002024000020046200461116002110910101600001000000100283117202118820043215160000102004720047200472004720047
160024200461501000008725800121280000128000062640000112002720046200463228001220800002024000020046200461116002110910101600001000000100283117202118920043215160000102004720047200472004720047
160024200461500000005125800121280104128000062640000112002720046200463228001220800002024000020046200461116002110910101600001000000100283116202118820043215160000102004720047200472004720047
160024200461501000004525800121280000128000062640000112003120046200463228001220800002024000020046200461116002110910101600001000003100283118202117720043215160000102004720047200472004720051

Test 6: throughput

Count: 16

Code:

  smlal v0.4s, v16.4h, v17.4h
  smlal v1.4s, v16.4h, v17.4h
  smlal v2.4s, v16.4h, v17.4h
  smlal v3.4s, v16.4h, v17.4h
  smlal v4.4s, v16.4h, v17.4h
  smlal v5.4s, v16.4h, v17.4h
  smlal v6.4s, v16.4h, v17.4h
  smlal v7.4s, v16.4h, v17.4h
  smlal v8.4s, v16.4h, v17.4h
  smlal v9.4s, v16.4h, v17.4h
  smlal v10.4s, v16.4h, v17.4h
  smlal v11.4s, v16.4h, v17.4h
  smlal v12.4s, v16.4h, v17.4h
  smlal v13.4s, v16.4h, v17.4h
  smlal v14.4s, v16.4h, v17.4h
  smlal v15.4s, v16.4h, v17.4h
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03mmu table walk data (08)191e373f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602044006130000004102516010010016000010016000050012800000400204003940039199733199971601002001600002004800004003940039111602011009910010016000010000010110116154004501600001004004940040400404004040049
1602044003930200004102516010010016000010016000050012800000400204003940048199733199971601002001600002004800004003940039111602011009910010016000010000910110116114003601600001004004040040400494004940040
16020440039299000041025160100100160000100160000620128000014002040039400391997331999716010020016000020048000040039400391116020110099100100160000100002110110116114003601600001004004040040400404004040040
16020440039299000041025160100100160000100160000500128000004002040039400391997331999716010020016000020048000040039400391116020110099100100160000100003610110116114003601600001004004040040400404004040040
16020440039300000041025160100100160000100160000500128000004002040039400391997331999716010020016000020048000040039400391116020110099100100160000100003910110116114003601600001004004040040400404004040040
16020440039300000050025160117100160000100160000500239899914002040048400391997331999716010020016000020048000040039400391116020110099100100160000100002110110116114003601600001004004940040400494004040040
160204400393000001741025160100100160000100160000500128000004002040039400391997331999716010020016000020048000040039400391116020110099100100160000100002710110116114003601600001004004040040400404004040040
16020440039300000175002516010010016000010016000053012800000400294003940039199733199971601002001600002004800004003940039111602011009910010016000010000310110116114003601600001004004940040400404004040040
1602044003930000006202516010010016001710016000050023989990400204004840039199733199971601002001600002004800004003940039111602011009910010016000010000010110116114003601600001004004040040400404004040040
16020440048300000041025160100100160017100160000500128000004002040048400391997331999716010020016000020048000040039400391116020110099100100160000100003010110116114003601600001004004040040400404004040040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)031e1f373f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fst unit uop (a7)l1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
16002440058299000236251600101016000010160000501280000014002040039400391999632001916001020160000204800004003940039111600211091010160000100030100256221016422116400364012160000104004040040400404004040040
1600244003929900052251600101016000010160000502398999114002040039400391999632001916001020160000204800004003940039111600211091010160000100201002562251642251040046409160000104004040040400404004040041
16002440039300013204725160010101600001016000050128000001400204003940049199963200191600102016000020480000400394003911160021109101016000010002110025621716422116400364018160000104004040050400404004040040
1600244003929900052251600101016000010160000501280000014002040039400391999632001916001020160000204800004003940039111600211091010160000100030100253226164121012400364012160000104004940049400404004040040
160024400393000005225160010101600001016000050128000001400204003940039199963200191600102016000020480000400394004911160021109101016000010003310025322816422129400362012160000104004040040400404004040040
1600244003930000052251600101016000010160000501280000014002040039400391999632001916001020160000204800004003940049111600211091010160000100027100256121016422105400364012160000104004040040400404004040040
16002440048300001746251600101016000010160000621280000014002040039400391999632002816001020160000204800004003940039111600211091010160000100010510022611101621161040046207160000104004040040400404004040040
1600244004830000178425160028101600001016000050128000001400214003940039199963200191600102016000020480000400394003911160021109101016000010002710025322616422510400364012160000104004040040400404004040040
1600244004830000052251600101016000010160000501280000014002040048400391999632001916001020160000204800004003940039111600211091010160000100063100256221016421610400364212160000104004040040400404004040040
1600244004830000052251600101016000010160000501280000014002940039400391999632001916001020160000204800004003940039111600211091010160000100030100226211016422117400364012160000104004040040400404004040040