Firestorm: SMLSL2 (by element, 4S) measurements

Code:

  smlsl2 v0.4s, v1.8h, v2.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	1	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	107	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	82	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	1	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	82	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	0	0	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  smlsl2 v0.4s, v1.8h, v2.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	0	0	0	1	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28272	7	28740	10100	200	10008	200	30024	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	1	1	1	717	0	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28272	7	28741	10100	200	10008	200	30024	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	1	1	1	718	0	0	16	0	0	29696	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	0	0	0	0	0	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	847	1	4	85	2	4	29885	10	10000	100	30324	30371	30360	30372	30322
10204	30324	227	1	0	6	7	924	176	0	4510	29512	162	10168	124	10056	124	10894	522	4286812	30234	30322	30371	28273	37	28874	11165	210	11484	228	33480	30372	30373	8	1	10201	100	99	100	100	10000	100	4	2	2	0	4	20003	0	0	0	0	869	1	2	33	2	2	29886	8	10000	100	30324	30370	30373	30133	30361
10204	30324	227	1	1	7	7	936	616	0	4596	29484	184	10156	113	10056	123	11043	615	4285455	30126	30368	30322	28291	39	28865	11168	222	11164	206	33495	30372	30370	8	1	10201	100	99	100	100	10000	100	0	2	0	1	0	19103	2	0	0	0	868	1	2	72	2	3	29894	8	10000	100	30373	30372	30368	30180	30369
10204	30374	227	0	0	0	0	0	0	0	61	29548	25	10100	100	10007	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	710	1	2	16	2	2	29634	0	10000	100	30038	30085	30038	30038	30038
10204	30037	225	0	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	710	1	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	224	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	0	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	3	0	0	640	5	16	3	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	0	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	2	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	0	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	3	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	726	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	0	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	156	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	0	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	536	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	0	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	4	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	156	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	0	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	18	0	313	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	0	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	0	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	2	16	3	3	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	0	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	640	3	16	3	3	29630	10000	10	30038	30083	30038	30038	30038

Test 3: Latency 1->2

Code:

  smlsl2 v0.4s, v0.8h, v1.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	12	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	30	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	1	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	27	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	18	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28816	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	42	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	21	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	33	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	30	89	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28816	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	27	61	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	224	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	1	2	29630	10000	10	30038	30038	30085	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10007	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	22	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	1	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	426	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	15	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	42	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28823	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	45	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	12	61	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038

Test 4: Latency 1->3

Code:

  smlsl2 v0.4s, v1.8h, v0.h[1]

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	180	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	15	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	732	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	3	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	51	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	0	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	4	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	15	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	15	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	15	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	0	0	0	0	0	12	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28841	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	27	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	18	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	39	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	18	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	24	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	21	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	640	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  smlsl2 v0.4s, v8.8h, v9.h[1]
  movi v1.16b, 0
  smlsl2 v1.4s, v8.8h, v9.h[1]
  movi v2.16b, 0
  smlsl2 v2.4s, v8.8h, v9.h[1]
  movi v3.16b, 0
  smlsl2 v3.4s, v8.8h, v9.h[1]
  movi v4.16b, 0
  smlsl2 v4.4s, v8.8h, v9.h[1]
  movi v5.16b, 0
  smlsl2 v5.4s, v8.8h, v9.h[1]
  movi v6.16b, 0
  smlsl2 v6.4s, v8.8h, v9.h[1]
  movi v7.16b, 0
  smlsl2 v7.4s, v8.8h, v9.h[1]

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20088	150	12	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	15	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	151	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20224	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10111	1	16	1	1	20061	0	160000	100	20168	20306	20065	20158	20065
160204	20064	150	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	151	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	39	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	963	25	80100	100	80000	100	80000	500	640000	0	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	0	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20071	150	0	9	0	45	25	80012	12	80000	12	80000	62	640000	1	1	5	20029	0	20052	20052	3	22	80012	20	80000	20	240000	20048	20052	1	1	160021	10	9	10	10	160000	10	0	0	10046	8	1	1	29	22	1	1	1	26	17	20045	2	16	160000	10	20049	20049	20049	20049	20049
160024	20048	150	0	0	1	74	25	80012	12	80000	12	80000	62	640000	1	1	0	20029	0	20048	20048	3	65	80012	20	80000	20	240000	20048	20048	1	1	160021	10	9	10	10	160000	10	0	0	10047	3	1	1	26	22	1	1	1	21	25	20045	2	16	160000	10	20049	20049	20049	20049	20049
160024	20048	150	0	6	1	74	25	80012	12	80000	12	80000	62	640000	1	1	5	20029	0	20050	20048	3	22	80012	20	80000	20	240000	20048	20048	1	1	160021	10	9	10	10	160000	10	1	0	10044	3	4	1	21	22	1	2	1	16	25	20049	2	16	160000	10	20049	20049	20049	20049	20049
160024	20052	150	1	0	0	74	25	80012	12	80000	12	80000	62	640000	0	0	0	20029	0	20052	20048	3	22	80012	20	80000	20	240000	20048	20048	1	1	160021	10	9	10	10	160000	10	0	0	10039	8	4	1	21	22	1	1	1	25	15	20045	2	16	160000	10	20049	20049	20049	20049	20049
160024	20048	151	1	0	1	74	25	80012	12	80000	12	80000	62	640000	1	0	0	20029	0	20052	20048	3	22	80012	20	80000	20	240000	20048	20048	1	1	160021	10	9	10	10	160000	10	0	0	10048	11	1	1	25	22	3	1	1	27	27	20045	2	16	160000	10	20049	20049	20049	20049	20049
160024	20052	150	1	0	0	45	25	80012	12	80000	12	80000	62	640000	1	0	5	20029	0	20048	20048	3	22	80012	20	80000	20	240000	20048	20048	1	1	160021	10	9	10	10	160000	10	0	0	10047	8	4	1	17	22	3	1	2	27	16	20045	2	16	160000	10	20049	20049	20049	20049	20049
160024	20048	150	0	18	1	74	25	80012	12	80000	12	80000	62	640000	1	0	5	20029	0	20048	20048	3	22	80012	20	80000	20	240000	20048	20048	1	1	160021	10	9	10	10	160000	10	0	0	10043	3	4	1	23	22	1	1	1	26	16	20045	2	16	160000	10	20049	20049	20049	20049	20049
160024	20048	150	1	3	0	45	25	80012	12	80000	12	80000	62	640000	1	0	5	20029	0	20052	20048	3	22	80012	20	80000	20	240000	20048	20048	1	1	160021	10	9	10	10	160000	10	0	0	10046	8	5	1	24	22	1	1	1	28	21	20045	2	31	160000	10	20049	20049	20049	20049	20049
160024	20048	150	1	33	0	74	25	80012	12	80000	12	80000	62	640000	1	1	5	20029	0	20048	20052	3	22	80012	20	80000	20	240000	20048	20048	1	1	160021	10	9	10	10	160000	10	0	0	10047	8	1	1	26	22	1	1	1	17	26	20045	2	16	160000	10	20049	20049	20049	20049	20049
160024	20048	150	1	15	0	74	25	80012	12	80000	12	80000	62	640000	1	0	5	20029	0	20052	20048	3	22	80012	20	80000	20	240000	20048	20048	1	1	160021	10	9	10	10	160000	10	0	0	10049	3	1	1	27	22	1	1	1	25	26	20045	2	16	160000	10	20049	20049	20049	20049	20049

Test 6: throughput

Count: 12

Code:

  smlsl2 v0.4s, v12.8h, v13.h[1]
  smlsl2 v1.4s, v12.8h, v13.h[1]
  smlsl2 v2.4s, v12.8h, v13.h[1]
  smlsl2 v3.4s, v12.8h, v13.h[1]
  smlsl2 v4.4s, v12.8h, v13.h[1]
  smlsl2 v5.4s, v12.8h, v13.h[1]
  smlsl2 v6.4s, v12.8h, v13.h[1]
  smlsl2 v7.4s, v12.8h, v13.h[1]
  smlsl2 v8.4s, v12.8h, v13.h[1]
  smlsl2 v9.4s, v12.8h, v13.h[1]
  smlsl2 v10.4s, v12.8h, v13.h[1]
  smlsl2 v11.4s, v12.8h, v13.h[1]

Initialization

  movi v12.16b, 13
  movi v13.16b, 14

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
120204	30147	225	0	0	0	41	0	25	120100	100	120000	100	120000	500	4399524	30020	31748	30039	14973	3	14997	120100	200	120000	200	360000	31748	30039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	7610	6	16	2	2	30036	120000	100	30040	31749	30040	30043	30040
120204	30039	225	0	6	0	41	0	25	120100	100	120000	100	120000	500	960000	31729	31748	30039	14973	3	16706	120100	200	120000	200	360000	30040	30039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	7610	2	16	2	2	30036	120000	100	31749	30040	31749	30040	30041
120204	30922	232	0	0	18	61	0	25	120118	100	120001	100	120000	500	960000	30020	30039	31748	16653	3	16706	120100	200	120000	200	360000	31748	30039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	7610	2	16	2	2	30036	120000	100	31749	30040	31749	30040	31749
120204	31748	225	0	0	0	41	6713	25	120118	100	120001	100	120000	500	960000	30021	30039	30040	14973	3	14997	120100	200	120000	200	360000	30039	30040	1	1	120201	100	99	100	100	120000	100	0	0	0	0	7610	2	16	2	2	31745	120000	100	30040	31749	30040	31749	30040
120204	30039	238	0	0	0	42	0	25	120100	100	120000	100	120000	500	4399524	30020	30039	31748	16653	3	14998	120100	200	120000	200	360000	31748	30039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	7610	2	16	2	2	30036	120000	100	31749	30040	31749	30040	30040
120204	30039	238	0	0	1	41	6713	25	120118	100	120000	100	120000	500	960000	30020	31748	30039	14973	3	14997	120100	200	120000	200	360000	30039	31748	1	1	120201	100	99	100	100	120000	100	0	0	0	0	7610	2	16	2	2	31745	120000	100	30040	31749	31739	30040	30040
120204	30039	238	0	0	0	41	6713	25	120118	100	120018	100	120000	500	4399524	30020	30039	31748	16653	3	14997	120100	200	120000	200	360000	30039	30042	1	1	120201	100	99	100	100	120000	100	0	0	0	0	7610	2	16	2	2	30036	120000	100	31749	30040	31749	30040	30040
120204	30039	225	0	0	17	61	0	25	120100	100	120000	100	120000	500	4399524	30020	30039	31748	16653	3	16706	120100	200	120000	200	360000	31748	30039	1	1	120201	100	99	100	100	120000	100	0	0	0	0	7610	2	16	2	2	30036	120000	100	31749	30040	31749	30040	31749
120204	31748	225	0	0	0	41	0	25	120100	100	120000	100	120000	500	4283622	30020	30039	30922	14973	3	16706	120100	200	120000	200	360000	31748	30039	1	1	120201	100	99	100	100	120000	100	4	0	0	0	7610	2	16	2	2	30036	120000	100	30783	30040	30040	30040	30040
120204	30039	225	0	0	0	186	6713	25	120118	100	120018	100	120120	500	960000	30065	30040	30039	14973	3	14997	120100	200	120000	200	360000	30039	30040	1	1	120201	100	99	100	100	120000	100	0	0	0	0	7610	2	16	2	2	30037	120000	100	31749	30040	30043	30041	30040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2503

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	c2	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
120024	30039	231	0	46	0	25	120010	10	120000	10	120000	50	960000	1	1	30020	30041	30039	14996	3	15019	120010	20	120000	20	360000	30039	30922	1	1	120021	10	9	10	10	120000	10	0	0	0	7522	3	1	1	19	16	2	1	1	12	12	30036	20	6	120000	10	30040	30923	30040	30040	30040
120024	30039	225	0	46	0	25	120010	10	120000	10	120000	50	960000	1	1	30022	30039	30039	14996	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	7522	3	1	1	13	16	2	1	1	8	13	30036	20	22	120000	10	30040	30040	30040	30040	30040
120024	30039	225	0	46	0	25	120010	10	120000	10	120000	50	960000	2	1	30020	30039	30039	14996	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	7522	3	1	1	13	16	2	1	1	13	9	30036	20	6	120000	10	30040	30040	30040	30040	30040
120024	30039	225	0	46	0	25	120010	10	120000	10	120000	50	960000	2	1	30020	30039	30039	14996	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	7522	3	1	1	12	16	2	1	1	8	14	30036	20	6	120000	10	30040	30040	30923	30040	30042
120024	30039	225	0	46	0	25	120010	10	120000	10	120000	50	960000	2	1	30020	30039	30039	14996	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	7522	3	1	1	12	16	2	1	1	14	13	30036	20	6	120000	10	30040	30040	30040	30040	30040
120024	30039	225	0	46	0	25	120010	10	120000	10	120000	50	990000	2	1	30020	30039	30039	14996	3	15902	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	7522	3	1	1	14	16	2	1	1	13	9	30036	20	6	120000	10	30040	30040	30040	30040	30040
120024	30039	225	0	46	0	25	120027	10	120000	10	120000	50	960000	2	1	30020	30041	30039	14996	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	7524	3	1	1	9	16	2	1	1	9	14	30036	20	6	120000	10	30040	30040	30040	30040	30040
120024	30039	225	0	46	0	25	120010	10	120000	10	120000	50	960000	2	1	30020	30039	30039	14996	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	7522	3	1	1	14	16	2	1	1	13	13	30036	20	6	120000	10	30040	30040	30040	30040	30040
120024	30039	225	0	46	0	25	120010	10	120000	10	120000	50	960000	2	1	30021	30039	30039	14996	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	7522	3	1	1	15	16	2	1	1	13	14	30086	20	6	120000	10	30040	30040	30040	30040	30040
120024	30039	225	0	46	0	25	120010	10	120000	10	120000	50	960000	2	1	30020	30039	30039	14996	3	15019	120010	20	120000	20	360000	30039	30039	1	1	120021	10	9	10	10	120000	10	0	0	0	7522	3	1	1	14	16	2	1	1	12	12	30036	20	6	120000	10	30040	30040	30040	30040	30040

SMLSL2 (by element, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations