Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SMLSL2 (vector, 8H)

Test 1: uops

Code:

  smlsl2 v0.8h, v1.16b, v2.16b
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372200103254825100010001000398313130183037303724153289510001000300030373037111001100073216112630100030383038303830383038
10043037230061254825100010001000398313130183037303724153289510001000300030373037111001100073116112630100030383038303830383038
10043037220061254825100010001000398313130183037303724153289510001000300030373037111001100073116112630100030383038303830383038
10043037230061254825100010001000398313130183037303724153289510001000300030373037111001100073116112630100030383038303830383038
10043037220061254825100010001000398313130183037303724153289510001000300030373037111001100073116112630100030383038303830383038
10043037230061254825100010001000398313130183037303724153289510001000300030373037111001100073116112630100030383038303830383038
10043037230061254825100010001000398313130183037303724153289510001000300030373037111001100073116112630100030383038303830383038
100430372300297254825100010001000398313130183037303724153289510001000300030373037111001100073116112630100030383038303830383038
10043037220961254825100010001000398313130183037303724153289510001000300030373037111001100073116112630100030383038303830383038
10043037230061254825100010001000398313130183037303724153289510001000300030373037111001100073116112630100030383038303830383038

Test 2: Latency 1->1

Code:

  smlsl2 v0.8h, v1.16b, v2.16b
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)033a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000071013162229634100001003003830038300383003830038
102043003722506129548251010010010000100100005004277313130018300373003728265328745101002001000020030000300373003711102011009910010010000100001271012162229634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000071012162229634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000071013162229634100001003003830038300383003830038
10204300372240612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000071012162229634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000071212162229634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000071012162229634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000071012162229634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000071012162229634100001003003830038300383003830038
10204300372250612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000071012162329634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722511016529548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100642816892963010000103003830038300383003830038
1002430037225110165295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001006421016762963010000103003830038300383003830038
1002430037225110165295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001006428169112963010000103003830038300383003830038
1002430037225110165295482510010101000010100005042773131300183003730037282873287671001020101722030000300373003711100211091010100001006429161092963010000103003830038300383003830038
100243003722511016529548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100642917992963010000103003830038300383003830038
1002430037225110165295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001006426161082963010000103003830038300383003830038
100243003722511016529548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100642716682963010000103003830038300383003830038
1002430037225110165295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001006429169102963010000103003830038300383003830038
100243003722511016529548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100642916872963010000103003830038300383003830038
100243003722511016529548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100642916992963010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  smlsl2 v0.8h, v0.16b, v1.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225000612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000000071021622296340100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000000071021622296340100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000002960071021622296340100001003003830038300383003830038
1020430037225000822954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000000071021622296340100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000010071021622296350100001003003830038300383003830038
1020430037224000612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000000071021622296340100001003003830038300383003830038
1020430037225100612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000000071021622296340100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010012030071021622296340100001003003830038300383003830038
1020430037225000612954825101001001000010010000552427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000000071021622296340100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000000071021622296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l1i tlb fill (04)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430227225000000266295482510010101000010100005042773133001830037300372828703287671001020100002030000300373003711100211091010100001000003644916101029630010000103003830038300383008430038
100243003722500001530266295212510010101000010100005042773133001830037300372828703287671001020100002030000300373003711100211091010100001000406644816101029630010000103003830038300383003830038
100243003722500000024262954825100101010000101000050427731330018300373003728287032876710010201000020300003003730037111002110910101000010001027386441016101029630010000103003830038300383003830038
10024300372260000002446295482510010101000010100005042773133001830037300372828703287671001020100002030000300373003711100211091010100001000000644516101029630010000103003830038300383003830038
1002430037225000000266295482510010101000010100005042773133001830037300372828703287671001020100002030000300373003711100211091010100001000000644516101029630010000103003830038300383003830038
100243003722500000026629548251001010100001010000504277313300183003730037282870328767100102010000203000030037300371110021109101010000100000064481681029630010000103003830038300383003830038
10024300372250000002662954825100101010000101000050427731330018300373003728287032876710010201000020300003003730037111002110910101000010020006441016101029630010000103003830038300383003830038
10024300372250000002662954825100101010000101000050427731330018300373003728287032876710010201000020300003003730037111002110910101000010000006441116101129630010000103003830038300383003830038
10024300372250000002662954825100101010000101000050427731330018300373003728287032876710010201000020300003003730037111002110910101000010000006441016101029630010000103003830038300383003830038
1002430037225000000266295482510010101000010100005042773133001830037300372828703287671001020100002030000300373003711100211091010100001000000644516101029630010000103003830038300383003830038

Test 4: Latency 1->3

Code:

  smlsl2 v0.8h, v1.16b, v0.16b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03181e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225000612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
10204300372250007222954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010006007101161129634100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722500012822954825101001001000010310000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
102043003722500017342954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038
10204300372250002512954825101311001000010010000500427731313001830037300372826532874510100200100002003000030037300371110201100991001001000010000007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225061295482510010101000010100005042773130300183003730037282873287671001020100002030000300373003711100211091010100001000189640216222963010000103003830038300383003830038
10024300372240612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710160201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372240612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000640217222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
1002430037225018662954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  smlsl2 v0.8h, v8.16b, v9.16b
  movi v1.16b, 0
  smlsl2 v1.8h, v8.16b, v9.16b
  movi v2.16b, 0
  smlsl2 v2.8h, v8.16b, v9.16b
  movi v3.16b, 0
  smlsl2 v3.8h, v8.16b, v9.16b
  movi v4.16b, 0
  smlsl2 v4.8h, v8.16b, v9.16b
  movi v5.16b, 0
  smlsl2 v5.8h, v8.16b, v9.16b
  movi v6.16b, 0
  smlsl2 v6.8h, v8.16b, v9.16b
  movi v7.16b, 0
  smlsl2 v7.8h, v8.16b, v9.16b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
160204200901500392580100100800001008000050064000012004520064200643228010020080000200240000200642006411160201100991001001600001000010111116112006101600001002006520065200652006520065
1602042022915012392580100100800001008000050064000012004520064200643228010020080000200240000200642006411160201100991001001600001000010111116112006101600001002006520065200652006520065
1602042006415003762580100100800001008000050064000012004520064200643228010020080000200240000200642006411160201100991001001600001000010111116112006101600001002006520065200652006520065
1602042006415005352580100100800001008000050064000012004520064200643228010020080000200240000200642006411160201100991001001600001000010111116112006101600001002006520065200652006520065
160204200641500392580100100800001008000050064000012004520064200643228010020080000200240000200642006411160201100991001001600001001310111116112006101600001002006520065200652006520065
160204200641500392580100100800001008000050064000012004520064200643228010020080000200240000200642006411160201100991001001600001001010111116112006101600001002006520065200652006520145
1602042006415003622580100100800001008000050064000012004520064200643228010020080000200240000200642006411160201100991001001600001000010111116112006101600001002006520065200652006520065
160204200641500392580100100800001008000050064000012004520064200643228010020080000200240000200642006411160201100991001001600001000010111116112006101600001002006520065200652006520065
1602042006415001232580100100800001008000050064000012004520064200643228010020080000200240000200642006411160201100991001001600001000010111116112006101600001002006520065200652006520065
160204200641500392580100100800001008000050064000012004520064200643228010020080000200240000200642006411160201100991001001600001000010111116112006101600001002006520065200652006520065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2507

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk data (08)1e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696b6d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accdcfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaec? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024200741501000145278001212800001280000626400001110200340200532005332280012208000020240000200532005311160021109101016000010000100441651028271113333200502211160000102005420054201202007620054
160024200531500060072278001212800001280000626400001110200340200532005332280012208000020240000200532005311160021109101016000010000100571381137271113639200502211160000102005420054200542005420054
1600242005315000001129278001212800001280000626400001110200340200532005332280012208000020240000200532005311160021109101016000010000100571371036271113637200502211160000102005420054200542005420054
16002420053150000001098278001212800001280000626400001110200340200532005332280012208000020240000200532005311160021109101016000010000100591381038271123434200502211160000102005420054200542005420054
160024200531510000151298001212800001280000626400001110200340200532005332280012208000020240000200532005311160021109101016000010030100631382030273123837200502211160000102005420054200542006320063
160024200621500000051278001212800001280000626400000110200340200622005332280012208000020240000200532005311160021109101016000010000100581391037361213837200592212160000102005420054200542005420054
1600242005315000000209298001212800001280000626400001110200340200532006232280012208000020240000200532005311160021109101016000010001100471381024271113625200502211160000102005420054200542006320063
160024200621500000145278001212800001280000626400001110200430200532005332280012208000020240000200622005311160021109101016000010030100561691032271122237200502212160000102006320054200632005420054
160024200531500000151278001212800001280000626400000110200340200532005332280012208000020240000200622005311160021109101016000010000100491381036273113335200502211160000102005420054200542005420063
160024200531500000070278001212800001280000626400001110200340200532005332280012208000020240000200622005311160021109101016000010000100571381037273113034200502211160000102005420054200542006320054

Test 6: throughput

Count: 16

Code:

  smlsl2 v0.8h, v16.16b, v17.16b
  smlsl2 v1.8h, v16.16b, v17.16b
  smlsl2 v2.8h, v16.16b, v17.16b
  smlsl2 v3.8h, v16.16b, v17.16b
  smlsl2 v4.8h, v16.16b, v17.16b
  smlsl2 v5.8h, v16.16b, v17.16b
  smlsl2 v6.8h, v16.16b, v17.16b
  smlsl2 v7.8h, v16.16b, v17.16b
  smlsl2 v8.8h, v16.16b, v17.16b
  smlsl2 v9.8h, v16.16b, v17.16b
  smlsl2 v10.8h, v16.16b, v17.16b
  smlsl2 v11.8h, v16.16b, v17.16b
  smlsl2 v12.8h, v16.16b, v17.16b
  smlsl2 v13.8h, v16.16b, v17.16b
  smlsl2 v14.8h, v16.16b, v17.16b
  smlsl2 v15.8h, v16.16b, v17.16b
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e373f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acbranch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602044005730000183025160100100160017100160000500128000004002940039400391997332000616010020016000020048000040039400491116020110099100100160000100000001011021611400361600001004004040050400404004040040
16020440039300012062025160100100160000100160000500128000014002040048400391997332000616010020016000020048000040049400481116020110099100100160000100100001011011611400361600001004004040050400404004040049
16020440048299001750025160100100160017100160000500243886514022940039400401997331999716010020016000020048000040040400481116020110099100100160000100203001011011611400461600001004004040040400404004040050
16020440048299001741025160100100160000100160000500239899904002940048400481997331999716010020016000020048000040040400401116020110099100100160000100000001011011611400451600001004004040049400494004040041
16020440039300001750025160100100160000100160000500131999804003040049400391997331999816010020016000020048000040049400391116020110099100100160000100000001011011611400451600001004005040040400404004040040
16020440040300001741025160100100160001100160000500128000004002040039400391997331999716010020016000020048000040048400481116020110099100100160000100000001011011611400361600001004005040049400404004140049
1602044004830000041025160117100160000100160000500239902704002140040400391997331999716010020016000020048000040039400391116020110099100100160000100000001011011611400361600001004004040050400404004040040
16020440039300000410251601011001600001001600005001320000040020400394003919973319997160100200160000200480000400394003911160201100991001001600001002300001011011611400451600001004004940049400494004940049
1602044004830000079025160100100160017100160000500128000004002940048400391997331999716010020016000020048000040049400481116020110099100100160000100000001011011611400371600001004004040049400404004140040
1602044003929900041025160100100160017100160000500128000014002040039400401997331999816010020016000020048000040039400391116020110099100100160000100000001011011611400461600001004004140040400414004040040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)0309191e373f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600244007030000017462516002712160017101600005012800001140020400394003919996320028160010201600002048000040039400391116002110910101600001001002231224162281182040036155160000104004040040400404004040040
160024400393000001846251600101016000010160000501280000014002040049400391999632001916001020160000204800004003940039111600211091010160000100100223111816432162040036155160000104005040050400404004040040
1600244003930000004625160010101600001016000050128000011400204003940039199963200191600102016000020480000400394003911160021109101016000010010022612181622221820400363010160000104004040040400404004040040
16002440039300000046251600101016001810160000501280000114002040039400391999632002916001020160000204800004003940049111600211091010160000100100223118162231182440036155160000104004040040400404004040040
16002440049299000046251600271016000010160000501280000114002040039400391999632001916001020160000204800004003940039111600211091010160000100100223111516222192140036155160000104004040040400504005040040
16002440049300000046251600101016001810160000501280000114002040039400391999632001916001020160000204800004003940039111600211091010160000100100223111816224262040046305160000104004040040400404004040040
160024400393000000522516001010160018101600005012800000140021400394003919996320019160010201600002048000040039400391116002110910101600001058100223111816219262040036155160000104005040040400404004040040
16002440039300010046251600101016000010160000501280000114002040049400391999632001916001020160000204800004003940039111600211091010160000100100223111816219162240036155160000104004040049400404004040040
16002440039299000046251600101016001810160000501280000114003040049400491999632001916001020160000204800004004940049111600211091010160000100100223111816218118840036155160000104004040040400404004040050
1600244004930000014625160010101600001016000050128000011400204004840039199963200191600102016000020480000400394004911160021109101016000010010022311816219218840046155160000104004040040400404004040040