Firestorm: SMLSL2 (vector, 8H) measurements

Code:

  smlsl2 v0.8h, v1.16b, v2.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	22	0	0	103	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	73	2	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	297	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	22	0	9	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	3000	3037	3037	1	1	1001	1000	73	1	16	1	1	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  smlsl2 v0.8h, v1.16b, v2.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	3	16	2	2	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	12	710	1	2	16	2	2	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	3	16	2	2	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	712	1	2	16	2	2	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	2	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	710	1	2	16	2	3	29634	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	1	1	0	1	65	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	642	8	16	8	9	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	1	0	1	65	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	642	10	16	7	6	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	1	0	1	65	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	642	8	16	9	11	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	1	0	1	65	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10172	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	642	9	16	10	9	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	1	0	1	65	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	642	9	17	9	9	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	1	0	1	65	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	642	6	16	10	8	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	1	0	1	65	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	642	7	16	6	8	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	1	0	1	65	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	642	9	16	9	10	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	1	0	1	65	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	642	9	16	8	7	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	1	1	0	1	65	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	642	9	16	9	9	29630	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  smlsl2 v0.8h, v0.16b, v1.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	2960	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	82	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	1	0	0	710	2	16	2	2	29635	0	10000	100	30038	30038	30038	30038	30038
10204	30037	224	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	1	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	1	2	0	3	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	552	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	2	16	2	2	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	simd prf full (72)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30227	225	0	0	0	0	0	0	2	66	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	3	644	9	16	10	10	29630	0	10000	10	30038	30038	30038	30084	30038
10024	30037	225	0	0	0	0	153	0	2	66	29521	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	4	0	6	644	8	16	10	10	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	2	426	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	1	0	2738	644	10	16	10	10	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	226	0	0	0	0	0	0	2	446	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	644	5	16	10	10	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	2	66	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	644	5	16	10	10	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	2	66	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	644	8	16	8	10	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	2	66	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	2	0	0	0	644	10	16	10	10	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	2	66	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	644	11	16	10	11	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	2	66	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	644	10	16	10	10	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	2	66	29548	25	10010	10	10000	10	10000	50	4277313	30018	30037	30037	28287	0	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	644	5	16	10	10	29630	0	10000	10	30038	30038	30038	30038	30038

Test 4: Latency 1->3

Code:

  smlsl2 v0.8h, v1.16b, v0.16b

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	722	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	6	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	1282	29548	25	10100	100	10000	103	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	1734	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038
10204	30037	225	0	0	0	251	29548	25	10131	100	10000	100	10000	500	4277313	1	30018	30037	30037	28265	3	28745	10100	200	10000	200	30000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	710	1	16	1	1	29634	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	189	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10160	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	224	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	17	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	1866	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	10000	20	30000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  smlsl2 v0.8h, v8.16b, v9.16b
  movi v1.16b, 0
  smlsl2 v1.8h, v8.16b, v9.16b
  movi v2.16b, 0
  smlsl2 v2.8h, v8.16b, v9.16b
  movi v3.16b, 0
  smlsl2 v3.8h, v8.16b, v9.16b
  movi v4.16b, 0
  smlsl2 v4.8h, v8.16b, v9.16b
  movi v5.16b, 0
  smlsl2 v5.8h, v8.16b, v9.16b
  movi v6.16b, 0
  smlsl2 v6.8h, v8.16b, v9.16b
  movi v7.16b, 0
  smlsl2 v7.8h, v8.16b, v9.16b

Initialization

  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20090	150	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20229	150	12	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	376	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	535	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	1	3	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	1	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20145
160204	20064	150	0	362	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	123	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065
160204	20064	150	0	39	25	80100	100	80000	100	80000	500	640000	1	20045	20064	20064	3	22	80100	200	80000	200	240000	20064	20064	1	1	160201	100	99	100	100	160000	100	0	0	10111	1	16	1	1	20061	0	160000	100	20065	20065	20065	20065	20065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2507

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6b	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	cd	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20074	150	1	0	0	0	1	45	27	80012	12	80000	12	80000	62	640000	1	1	10	20034	0	20053	20053	3	22	80012	20	80000	20	240000	20053	20053	1	1	160021	10	9	10	10	160000	10	0	0	0	10044	16	5	1	0	28	27	1	1	1	33	33	20050	2	21	1	160000	10	20054	20054	20120	20076	20054
160024	20053	150	0	0	6	0	0	72	27	80012	12	80000	12	80000	62	640000	1	1	10	20034	0	20053	20053	3	22	80012	20	80000	20	240000	20053	20053	1	1	160021	10	9	10	10	160000	10	0	0	0	10057	13	8	1	1	37	27	1	1	1	36	39	20050	2	21	1	160000	10	20054	20054	20054	20054	20054
160024	20053	150	0	0	0	0	1	129	27	80012	12	80000	12	80000	62	640000	1	1	10	20034	0	20053	20053	3	22	80012	20	80000	20	240000	20053	20053	1	1	160021	10	9	10	10	160000	10	0	0	0	10057	13	7	1	0	36	27	1	1	1	36	37	20050	2	21	1	160000	10	20054	20054	20054	20054	20054
160024	20053	150	0	0	0	0	0	1098	27	80012	12	80000	12	80000	62	640000	1	1	10	20034	0	20053	20053	3	22	80012	20	80000	20	240000	20053	20053	1	1	160021	10	9	10	10	160000	10	0	0	0	10059	13	8	1	0	38	27	1	1	2	34	34	20050	2	21	1	160000	10	20054	20054	20054	20054	20054
160024	20053	151	0	0	0	0	1	51	29	80012	12	80000	12	80000	62	640000	1	1	10	20034	0	20053	20053	3	22	80012	20	80000	20	240000	20053	20053	1	1	160021	10	9	10	10	160000	10	0	3	0	10063	13	8	2	0	30	27	3	1	2	38	37	20050	2	21	1	160000	10	20054	20054	20054	20063	20063
160024	20062	150	0	0	0	0	0	51	27	80012	12	80000	12	80000	62	640000	0	1	10	20034	0	20062	20053	3	22	80012	20	80000	20	240000	20053	20053	1	1	160021	10	9	10	10	160000	10	0	0	0	10058	13	9	1	0	37	36	1	2	1	38	37	20059	2	21	2	160000	10	20054	20054	20054	20054	20054
160024	20053	150	0	0	0	0	0	209	29	80012	12	80000	12	80000	62	640000	1	1	10	20034	0	20053	20062	3	22	80012	20	80000	20	240000	20053	20053	1	1	160021	10	9	10	10	160000	10	0	0	1	10047	13	8	1	0	24	27	1	1	1	36	25	20050	2	21	1	160000	10	20054	20054	20054	20063	20063
160024	20062	150	0	0	0	0	1	45	27	80012	12	80000	12	80000	62	640000	1	1	10	20043	0	20053	20053	3	22	80012	20	80000	20	240000	20062	20053	1	1	160021	10	9	10	10	160000	10	0	3	0	10056	16	9	1	0	32	27	1	1	2	22	37	20050	2	21	2	160000	10	20063	20054	20063	20054	20054
160024	20053	150	0	0	0	0	1	51	27	80012	12	80000	12	80000	62	640000	0	1	10	20034	0	20053	20053	3	22	80012	20	80000	20	240000	20062	20053	1	1	160021	10	9	10	10	160000	10	0	0	0	10049	13	8	1	0	36	27	3	1	1	33	35	20050	2	21	1	160000	10	20054	20054	20054	20054	20063
160024	20053	150	0	0	0	0	0	70	27	80012	12	80000	12	80000	62	640000	1	1	10	20034	0	20053	20053	3	22	80012	20	80000	20	240000	20062	20053	1	1	160021	10	9	10	10	160000	10	0	0	0	10057	13	8	1	0	37	27	3	1	1	30	34	20050	2	21	1	160000	10	20054	20054	20054	20063	20054

Test 6: throughput

Count: 16

Code:

  smlsl2 v0.8h, v16.16b, v17.16b
  smlsl2 v1.8h, v16.16b, v17.16b
  smlsl2 v2.8h, v16.16b, v17.16b
  smlsl2 v3.8h, v16.16b, v17.16b
  smlsl2 v4.8h, v16.16b, v17.16b
  smlsl2 v5.8h, v16.16b, v17.16b
  smlsl2 v6.8h, v16.16b, v17.16b
  smlsl2 v7.8h, v16.16b, v17.16b
  smlsl2 v8.8h, v16.16b, v17.16b
  smlsl2 v9.8h, v16.16b, v17.16b
  smlsl2 v10.8h, v16.16b, v17.16b
  smlsl2 v11.8h, v16.16b, v17.16b
  smlsl2 v12.8h, v16.16b, v17.16b
  smlsl2 v13.8h, v16.16b, v17.16b
  smlsl2 v14.8h, v16.16b, v17.16b
  smlsl2 v15.8h, v16.16b, v17.16b

Initialization

  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	37	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40057	300	0	0	1	83	0	25	160100	100	160017	100	160000	500	1280000	0	40029	40039	40039	19973	3	20006	160100	200	160000	200	480000	40039	40049	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	2	16	1	1	40036	160000	100	40040	40050	40040	40040	40040
160204	40039	300	0	12	0	62	0	25	160100	100	160000	100	160000	500	1280000	1	40020	40048	40039	19973	3	20006	160100	200	160000	200	480000	40049	40048	1	1	160201	100	99	100	100	160000	100	1	0	0	0	0	10110	1	16	1	1	40036	160000	100	40040	40050	40040	40040	40049
160204	40048	299	0	0	17	50	0	25	160100	100	160017	100	160000	500	2438865	1	40229	40039	40040	19973	3	19997	160100	200	160000	200	480000	40040	40048	1	1	160201	100	99	100	100	160000	100	2	0	3	0	0	10110	1	16	1	1	40046	160000	100	40040	40040	40040	40040	40050
160204	40048	299	0	0	17	41	0	25	160100	100	160000	100	160000	500	2398999	0	40029	40048	40048	19973	3	19997	160100	200	160000	200	480000	40040	40040	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	1	16	1	1	40045	160000	100	40040	40049	40049	40040	40041
160204	40039	300	0	0	17	50	0	25	160100	100	160000	100	160000	500	1319998	0	40030	40049	40039	19973	3	19998	160100	200	160000	200	480000	40049	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	1	16	1	1	40045	160000	100	40050	40040	40040	40040	40040
160204	40040	300	0	0	17	41	0	25	160100	100	160001	100	160000	500	1280000	0	40020	40039	40039	19973	3	19997	160100	200	160000	200	480000	40048	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	1	16	1	1	40036	160000	100	40050	40049	40040	40041	40049
160204	40048	300	0	0	0	41	0	25	160117	100	160000	100	160000	500	2399027	0	40021	40040	40039	19973	3	19997	160100	200	160000	200	480000	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	1	16	1	1	40036	160000	100	40040	40050	40040	40040	40040
160204	40039	300	0	0	0	41	0	25	160101	100	160000	100	160000	500	1320000	0	40020	40039	40039	19973	3	19997	160100	200	160000	200	480000	40039	40039	1	1	160201	100	99	100	100	160000	100	23	0	0	0	0	10110	1	16	1	1	40045	160000	100	40049	40049	40049	40049	40049
160204	40048	300	0	0	0	79	0	25	160100	100	160017	100	160000	500	1280000	0	40029	40048	40039	19973	3	19997	160100	200	160000	200	480000	40049	40048	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	1	16	1	1	40037	160000	100	40040	40049	40040	40041	40040
160204	40039	299	0	0	0	41	0	25	160100	100	160017	100	160000	500	1280000	1	40020	40039	40040	19973	3	19998	160100	200	160000	200	480000	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	10110	1	16	1	1	40046	160000	100	40041	40040	40041	40040	40040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	19	1e	37	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40070	300	0	0	0	17	46	25	160027	12	160017	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20028	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	10022	3	1	2	24	16	2	28	1	18	20	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	18	46	25	160010	10	160000	10	160000	50	1280000	0	1	40020	40049	40039	19996	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	10022	3	1	1	18	16	4	32	1	6	20	40036	15	5	160000	10	40050	40050	40040	40040	40040
160024	40039	300	0	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	10022	6	1	2	18	16	2	22	2	18	20	40036	30	10	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	0	46	25	160010	10	160018	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20029	160010	20	160000	20	480000	40039	40049	1	1	160021	10	9	10	10	160000	10	0	10022	3	1	1	8	16	2	23	1	18	24	40036	15	5	160000	10	40040	40040	40040	40040	40040
160024	40049	299	0	0	0	0	46	25	160027	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	10022	3	1	1	15	16	2	22	1	9	21	40036	15	5	160000	10	40040	40040	40050	40050	40040
160024	40049	300	0	0	0	0	46	25	160010	10	160018	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	10022	3	1	1	18	16	2	24	2	6	20	40046	30	5	160000	10	40040	40040	40040	40040	40040
160024	40039	300	0	0	0	0	52	25	160010	10	160018	10	160000	50	1280000	0	1	40021	40039	40039	19996	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	58	10022	3	1	1	18	16	2	19	2	6	20	40036	15	5	160000	10	40050	40040	40040	40040	40040
160024	40039	300	0	1	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40049	40039	19996	3	20019	160010	20	160000	20	480000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	10022	3	1	1	18	16	2	19	1	6	22	40036	15	5	160000	10	40040	40049	40040	40040	40040
160024	40039	299	0	0	0	0	46	25	160010	10	160018	10	160000	50	1280000	1	1	40030	40049	40049	19996	3	20019	160010	20	160000	20	480000	40049	40049	1	1	160021	10	9	10	10	160000	10	0	10022	3	1	1	18	16	2	18	1	18	8	40036	15	5	160000	10	40040	40040	40040	40040	40050
160024	40049	300	0	0	0	1	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40048	40039	19996	3	20019	160010	20	160000	20	480000	40039	40049	1	1	160021	10	9	10	10	160000	10	0	10022	3	1	1	8	16	2	19	2	18	8	40046	15	5	160000	10	40040	40040	40040	40040	40040

SMLSL2 (vector, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations