Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SMLSL (vector, 8H)

Test 1: uops

Code:

  smlsl v0.8h, v1.8b, v2.8b
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372306125482510001000100039831303018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
1004303723059025484910001000100039831303018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831303018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831303018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831303018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831303018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372306125482510001000100039831303018303730372415328951000100030003037303711100110001073116112630100030383038303830383038
100430372306125482510001000100039831303018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372208225482510001000100039831303018303730372415328951000100030003037303711100110000073116112630100030383038303830383038
100430372206125482510001000100039831303018303730372415328951000100030003037303711100110000073116112630100030383038303830383038

Test 2: Latency 1->1

Code:

  smlsl v0.8h, v1.8b, v2.8b
  movi v0.16b, 1
  movi v1.16b, 2
  movi v2.16b, 3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722400612954825101001001000010010000500427731303001830037300372827262874110100200100082003002430037300371110201100991001001000010000011171800161029647100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372827262874110100200100082003002430037300371110201100991001001000010000011171700160029646100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010020000071002162229706100001003008330038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010001000071012163229634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000000071212162229634100001003003830072300383003830038
102043003722560612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000000071012162229634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000000071012163229634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000000071212162229634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000000071012162229634100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826532874510100200100002003000030037300371110201100991001001000010000000071012162229634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722502512954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000640316222963010000103003830038300383003830038
100243003722501512954825100101010000101000050427731303001830037300372831032876710010201000020300003003730037111002110910101000010000640216232963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000640216232963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000640216322963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010100640316222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000640216232963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000640216322963010000103003830038300383003830038
10024300372240612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000640316222963010000103003830038300383003830038
10024300372250612954825100101010000101000050427731303001830037300372828732876710010201000020300003003730037111002110910101000010000640216222963010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  smlsl v0.8h, v0.8b, v1.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)a9acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037224061295482510100100100001001000050042773131300183003730037282650328745101002001000020030000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773131300183003730037282650328745101002001000020030000300373003711102011009910010010000100000007101161129634100001003003830038300383008530038
1020430037225961295482510100100100001001000050042773131300183003730037282650328745101002001000020030000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773131300183003730037282650328745101002001000020030000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773131300183003730037282650328745101002001000020030000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773131300183003730037282650328745101002001000020030000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773131300183003730037282650328745101002001000020030000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
1020430037224061295482510100100100001001000050042773131300183003730037282650328745101002001000020030000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773131300183003730037282650328745101002001000020030000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038
1020430037225061295482510100100100001001000050042773131300183003730037282657328745101002001000020030000300373003711102011009910010010000100000007101161129634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)0918191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500000061295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000006402162229630010000103003830038300383003830038
100243003722500000061295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000006402162229630010000103003830038300383003830038
100243003722500000061295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000006402162229630010000103003830038300383003830038
100243003722500000061295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000006402162229630010000103003830038300383003830038
100243003722500009061295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000006402162229630010000103003830038300383003830038
1002430037225000015061295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000006402162229630010000103003830038300383003830038
100243003722400000061295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000006402162229630010000103003830038300383003830038
100243003722500000061295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001001006402162229630010000103003830038300383003830038
100243003722400000061295484410010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000006402162229630010000103003830038300383003830038
100243003722400000061295482510010101000010100005042773131300183003730037282873287671001020100002030000300373003711100211091010100001000006402162229630010000103003830038300383003830038

Test 4: Latency 1->3

Code:

  smlsl v0.8h, v1.8b, v0.8b
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250000000061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071013411296340100001003003830038300383003830038
1020430037225000000001032954825101001001000010010000500427731303001830037300372826510287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038
10204300372250000000061295482510100100100001001000050042773130300183008530085282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300853008530038
10204300372250000000061295482510100100100001001014950042773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038301343003830038
1020430037225000001200103295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000103071011611296340100001003003830038300383003830038
10204300372240010000061295482510100100100001001000050042773131300183022930037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830228
102043003722500000210061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001004000000071011611296340100001003003830038300383003830038
10204300372250000000061295482510100100100001001000050042773130300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830075300863003830038
10204300372250000000061295482510100100100001001000050042773130300543003730037282653287451010020010000200300003003730037511020110099100100100001000000000071021611296340100001003003830038300383003830038
102043003722500000120082295482510100100100001001000066142773131300183003730037282653287451010020010000200300003003730037111020110099100100100001000000000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372251000000006629548251001010100001010000504277313130018300373003728287328767100122010000203000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
10024300372250000000006129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
100243003722500000000025129548251001010100001010000504277313030018300373003728287328767100122010000203000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
100243003722500000000069029548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
10024300372250000000006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
10024300372250000000006129548251001010100001010000504277313030018300373003728287328767100102010000203000030085300371110021109101010000100000006402162229630010000103003830038300383003830038
10024300372250000000006129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100000006422163529632010000103003830038300383003830038
10024300372250000000006129548251001010100001010000504277313030018300373003728287328767100102010000203000030037300371110021109101010000100000006422162229630010000103003830038300383003830038
100243003722500000000072729548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000006402162229630010000103003830038300383003830038
10024300372250000000006129548251001010100001010000504277313130018300373003728287328767100102010000203000030037300371110021109101010000100000006402162229630010000103003830038300383003830038

Test 5: throughput

Count: 8

Code:

  movi v0.16b, 0
  smlsl v0.8h, v8.8b, v9.8b
  movi v1.16b, 0
  smlsl v1.8h, v8.8b, v9.8b
  movi v2.16b, 0
  smlsl v2.8h, v8.8b, v9.8b
  movi v3.16b, 0
  smlsl v3.8h, v8.8b, v9.8b
  movi v4.16b, 0
  smlsl v4.8h, v8.8b, v9.8b
  movi v5.16b, 0
  smlsl v5.8h, v8.8b, v9.8b
  movi v6.16b, 0
  smlsl v6.8h, v8.8b, v9.8b
  movi v7.16b, 0
  smlsl v7.8h, v8.8b, v9.8b
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)03181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
16020420089151003925801001008000010080000500640000200452006420064322801002008000020024000020064200641116020110099100100160000100001011421622200611600001002006520065200652006520065
16020420064150003925801001008000010080000500640000200452006420064322801002008000020024000020064200641116020110099100100160000100001011221622200611600001002006520065200652006520065
1602042006415004143925801001008000010080000500640000200452006420064322801002008000020024000020064200641116020110099100100160000100001011221622200611600001002013520065200652006520065
16020420064150003925801001008000010080000500640000200452006420064322801002008000020024000020064200641116020110099100100160000100001011321622200611600001002006520065200652006520065
1602042006415003393925801001008000010080000500640000200452006420064322801002008000020024000020064200641116020110099100100160000100001011221622200611600001002006520065200652006520065
16020420064151003925801001008000010080000500640000200452006420064322801002008000020024000020064200641116020110099100100160000100001011221622200611600001002006520065200652006520065
16020420064150093925801001008000010080000500640000200452006420064322801002008000020024000020064200641116020110099100100160000100001011441622200611600001002006520065200652006520065
1602042006415003243925801001008000010080000500640000200452006420064322801002008000020024000020064200641116020110099100100160000100001011221622200611600001002006520065200652006520065
1602042006415002673925801001008000010080000500640000200452006420064322801002008000020024000020064200641116020110099100100160000100001011321622200611600001002006520065200652006520065
16020420064150103925801001008000010080000500640000200452006420064322801002008000020024000020064200641116020110099100100160000100001011221622200611600001002006520065200652006520065

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acc2cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600242006715100051258001212800001280000626400000152003120050200503228001220800002024000020046200461116002110910101600001000001003311426264225620047231160000102005320053200472005120051
160024200501501005125800121280000128000062640000215200312005020050322800122080000202400002005220046111600211091010160000100000100288315202116820049215160000102004720047200472004720047
16002420046150104207925800121280000128000062640000215200312005220050322800122080000202400002005020052111600211091010160000100000100318318202116720043215160000102004720047200472004720047
1600242004615000372452580012128000012800006264000031520027200462004610428001220800002024000020046200461116002110910101600001000001003011315242117720043215160000102004720047200472004720047
1600242005015000071025800121280000128000062640000215200312004620046322800122080000202400002004620046111600211091010160000100000100318316202117720043230160000102004720047200472004720047
160024200461500004525800121280000128000062640000015200272004620046322800122080000202400002004620046111600211091010160000100000100288315202117720043215160000102004720047200472004720047
160024200461500004525800121280000128000062640000315200272004620046322800122080000202400002004620046111600211091010160000100000100318317202117820043215160000102004720047200512004720047
160024200461500004564800121280000128000062640000315200272004620046322800122080000202400002004620046111600211091010160000100000100308318202118820043215160000102004720047200472004720047
160024200501500004525800121280000128000062640000315200272004620046322800122080000202400002004620046111600211091010160000100000100308316202115820043215160000102004720047200472004720047
1600242004615100045258001212800001280000626400002152002720046200463228001220800002024000020046200461116002110910101600001000001003311427243225620047230160000102005120051200512005120051

Test 6: throughput

Count: 16

Code:

  smlsl v0.8h, v16.8b, v17.8b
  smlsl v1.8h, v16.8b, v17.8b
  smlsl v2.8h, v16.8b, v17.8b
  smlsl v3.8h, v16.8b, v17.8b
  smlsl v4.8h, v16.8b, v17.8b
  smlsl v5.8h, v16.8b, v17.8b
  smlsl v6.8h, v16.8b, v17.8b
  smlsl v7.8h, v16.8b, v17.8b
  smlsl v8.8h, v16.8b, v17.8b
  smlsl v9.8h, v16.8b, v17.8b
  smlsl v10.8h, v16.8b, v17.8b
  smlsl v11.8h, v16.8b, v17.8b
  smlsl v12.8h, v16.8b, v17.8b
  smlsl v13.8h, v16.8b, v17.8b
  smlsl v14.8h, v16.8b, v17.8b
  smlsl v15.8h, v16.8b, v17.8b
  movi v16.16b, 17
  movi v17.16b, 18

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f373f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9accfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
16020440060300000000525025160100100160001100160000500239899913400304003940039199733199971601002001600002004800004003940049111602011009910010016000010000000101103216224003601600001004005040040400724004040040
16020440040300100001751025160100100160000100160000560172394910400204003940040199733200291601002001600002004800004004940039111602011009910010016000010000000101100216224003701600001004004040040400404005040040
1602044004929900000050025160100100160000100160000500239899900400204004040049199803200071601002001600002004800004003940039111602011009910010016000010000000101100216224003601600001004004040040400504004040049
16020440039300000001741025160100100160000100160000500239899900400204003940039199733199971601002001600002004800004004840039111602011009910010016000010000000101100216224003701600001004015240040400404004040040
160204400493001000104174102516011710016006110016000050012800000040020400394003919973319997160100200160000200480000400394009111160201100991001001600001000012623101100216224003601600001004004040040400504004040041
16020440039300000001792025160117100160000100160000500128000000400304003940039199733199971601002001600002004800004003940049111602011009910010016000010000000101100216224003601600001004004940040400404004040041
160204400393000000061612525160100100160017100160000500128000000400204004940039199733199971601002001600002004800004003940040111602011009910010016000010000000101100216224003601600001004004040050400404007240040
16020440039300000006141025160100100160000100160000500128000000400204003940039199733199971601002001600002004800004003940039111602011009910010016000010000000101100216224004501600001004005040049400724004040050
1602044003930000000051025160100100160000100160000500132000000400304004040039199733199971601002001600002004800004004040039111602011009910010016000010000100101100216224003701600001004004040041400404004040040
16020440049300000000516025160100100160000100160000500131999900400204003940048199733199981601002001600002004800004004840039111602011009910010016000010000000101100216224004501600001004004940049400494004940050

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss data (0b)18191e373f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)dfe0? int output thing (e9)eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024400403000000000462516001010160000101600005012800003104002040039400401999632001916001020160000204800004004940049111600211091010160000100010022841616211430400360206160000104004040040400404004040040
160024400392993000000462516001010160000101600005012800002154002040039400391999632001916001020160000204800004003940039111600211091010160000100010022851316211340400360206160000104004040050400504004040050
1600244003930010000018462516001010160000101600005012800002154002040049400491999632001916001020160000204800004003940039111600211091010160000100010022851316411340400360206160000104004040040400404004040040
1600244003930010000005225160010101600001016000050128000021540030400394003919996320019160010201600002048000040039400481116002110910101600001000100248624164224404003604014160000104004040040400404004040040
1600244003930010000002362516011910160000101600005024388651154002040039400391999632002016001020160000204800004003940039111600211091010160000100010022851316212440400370406160000104004040040400404004040040
160024400493001000000462516001010160018101600005512800002154002040039400391999632001916001020160000204800004003940039111600211091010160000100010024851416222340400360206160000104004040050400504004040050
1600244003930010000005625160010101600001016000050128000021540020400394003919996320019160010201600002048000040039400391116002110910101600001000100221151316211440400360406160000104005040040400404004040040
160024400493001002200664325160028101600001016000050128000011540157400394003919996320019160010201602032048031840178401573116002110910101600001000100221162316412640401712206160000104004040040400404004040040
1600244003930010000005225160010101600181016000050243886521540020400404003919996320029160010201600002048000040039400491116002110910101600001000100228514162114304003602012160000104004040040400404004040040
160024400402992000000832516001010160000101600005012800002154003040049400391999632002816001020160000204800004004940049111600211091010160000100010022851416211430400360206160000104004040040400494004040040