Firestorm: SMOV (B to W) measurements

Code:

  smov w0, v0.b[1]

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d tlb access (a0)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	538	5	0	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	0	73	0	16	535	1000	1000	539	539	539	539	539
1004	538	4	0	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	0	73	0	16	535	1000	1000	539	539	539	539	539
1004	538	4	0	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	3	73	0	16	535	1000	1000	539	539	539	539	539
1004	538	4	0	0	64	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	0	73	0	16	535	1000	1000	539	539	539	539	539
1004	538	4	0	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	8	0	73	0	16	535	1000	1000	539	539	539	539	539
1004	538	4	0	12	64	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	3	73	0	16	535	1000	1000	539	539	539	539	539
1004	538	4	0	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	0	73	0	16	535	1000	1000	539	539	539	539	539
1004	538	4	0	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	0	73	0	16	535	1000	1000	539	539	539	539	539
1004	538	4	0	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	0	73	0	16	535	1000	1000	539	539	539	539	539
1004	538	4	0	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	0	73	0	16	535	1000	1000	539	539	539	539	539

Test 2: Latency 1->2 roundtrip

Code:

  smov w0, v0.b[1]
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20204	100038	776	0	0	0	0	0	0	0	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580404	100013	100038	100038	96907	6	97551	20100	200	10004	10004	200	10004	10004	100041	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	1	1	1	1317	0	16	0	0	99646	10000	10000	10100	100039	100039	100039	100039	100039
20204	100038	775	0	0	0	0	0	0	0	100025	89561	44	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	100013	100038	100038	96907	6	97492	20100	202	10004	10004	200	10004	10004	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	1	0	3	0	1	1	1	1317	0	16	0	0	99646	10000	10000	10100	100039	100039	100039	100042	100123
20204	100038	775	0	0	0	0	0	0	0	100023	89561	25	30100	10100	10000	10002	100	10000	10000	500	4778481	5580349	100013	100038	100038	96900	3	97496	20100	200	10000	10000	202	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	16	1	1	99697	10000	10000	10100	100039	100039	100039	100039	100039
20204	100038	775	0	0	0	0	0	0	0	100023	89562	25	30100	10100	10000	10000	100	10059	10000	500	4778481	5580349	100013	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	16	1	1	99642	10000	10000	10100	100039	100039	100041	100039	100039
20204	100067	776	0	0	0	0	0	0	0	100023	89561	25	30100	10100	10000	10000	100	10000	10050	500	4781157	5580349	100013	100038	100198	96943	3	97617	20334	200	10000	10000	202	10483	11239	101811	100207	4	1	20201	100	99	100	10100	10000	100	2	0	10006	0	2	23725	0	0	0	0	1349	2	25	1	1	99703	10010	10000	10100	100121	100124	100123	100039	100121
20204	100130	775	0	0	0	1	0	0	0	100108	89651	45	30123	10120	10003	10002	100	10119	10000	581	4778481	5632205	100013	100041	100038	96901	3	97496	20100	200	10000	10000	200	10000	10000	100038	100040	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	16	1	1	99637	10000	10000	10100	100039	100039	100039	100039	100039
20204	100038	776	0	0	0	0	12	0	0	100023	89562	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	100013	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	3	0	0	0	0	1310	1	16	1	1	99637	10000	10000	10100	100039	100039	100039	100039	100039
20204	100038	775	0	0	0	0	0	0	0	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	100014	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	3	0	0	0	0	1310	1	16	1	1	99637	10000	10000	10100	100039	100039	100039	100041	100042
20204	100038	776	0	0	0	0	36	0	0	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	100016	100040	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100039	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	3	0	0	0	0	1310	1	16	1	1	99637	10000	10000	10100	100039	100039	100039	100039	100039
20204	100038	776	0	0	0	0	0	0	0	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778625	5580349	100013	100039	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10001	0	0	0	0	0	0	0	1310	1	16	1	1	99637	10000	10000	10100	100039	100039	100039	100039	100039

1000 unrolls and 10 iterations

Result (median cycles for code): 10.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	50	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	79	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ec	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20024	100038	749	0	0	0	0	0	0	0	0	100024	89561	0	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	0	100015	100041	100038	96922	3	97520	20010	0	20	10000	10000	20	10000	10000	100038	100041	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	1	0	0	0	0	0	1270	2	16	2	2	99637	10000	0	10000	10010	100039	100039	100039	100039	100039
20024	100038	775	0	0	0	0	0	0	0	0	100023	89561	0	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	0	100013	100038	100038	96922	3	97518	20010	0	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	0	0	1270	2	16	2	2	99637	10000	0	10000	10010	100039	100039	100039	100039	100041
20024	100039	776	0	0	0	0	0	0	0	0	100023	89561	0	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	0	100013	100038	100038	96923	3	97518	20010	0	20	10000	10000	20	10000	10000	100041	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	0	0	1270	2	16	2	2	99637	10000	0	10000	10010	100039	100039	100039	100039	100039
20024	100038	775	0	0	0	0	0	0	0	0	100023	89561	0	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	0	100013	100038	100038	96922	3	97518	20010	0	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	3	0	0	0	1270	2	16	1	1	99637	10000	0	10000	10010	100039	100041	100039	100039	100042
20024	100039	775	0	0	0	0	0	0	0	0	100023	89561	0	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	0	100013	100041	100039	96922	3	97518	20010	0	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	1	0	0	0	0	0	1270	2	16	2	2	99637	10000	0	10000	10010	100039	100042	100039	100039	100042
20024	100038	775	0	0	0	0	0	132	0	0	100023	89561	0	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5579066	0	0	100013	100038	100038	96923	8	97518	20010	0	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	1	0	0	0	0	0	1270	2	16	1	1	99637	10000	0	10000	10010	100039	100039	100126	100039	100039
20024	100041	776	0	0	0	0	0	0	0	0	100024	89603	0	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5579064	0	0	100014	100038	100038	96922	3	97518	20010	0	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	1	0	0	0	0	1	1270	2	16	2	2	99637	10000	0	10000	10010	100040	100039	100039	100039	100039
20024	100039	776	0	0	0	0	0	12	0	0	100023	89562	0	25	30010	10010	10000	10000	10	10060	10000	50	4778625	5578954	0	0	100013	100038	100038	96922	3	97518	20010	0	20	10000	10000	20	10000	10000	100123	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	0	0	1270	2	16	2	2	99637	10000	0	10000	10010	100039	100040	100039	100039	100039
20024	100038	775	0	0	0	0	0	0	0	0	100025	89561	0	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	0	100013	100038	100041	96922	3	97518	20010	0	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	0	0	1270	2	16	2	2	99637	10000	0	10000	10010	100039	100039	100039	100039	100039
20024	100038	776	0	0	0	0	0	0	0	0	100023	89561	0	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5579009	0	0	100013	100038	100039	96922	8	97518	20010	0	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	1	0	0	0	0	0	1859	2	16	2	1	99637	10000	0	10000	10010	100039	100039	100039	100046	100129

Test 3: throughput

Count: 8

Code:

  smov w0, v8.b[1]
  smov w1, v8.b[1]
  smov w2, v8.b[1]
  smov w3, v8.b[1]
  smov w4, v8.b[1]
  smov w5, v8.b[1]
  smov w6, v8.b[1]
  smov w7, v8.b[1]

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	40053	322	0	0	24	32	25	160100	80100	80084	100	80004	500	640024	40019	40038	40108	29976	6	30037	80104	200	80111	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	2	1	1	1	5117	0	0	16	0	0	40091	80000	80100	40039	40039	40039	40039	40039
80204	40038	322	0	0	0	787	43	160100	80100	80000	100	80004	500	640024	40019	40038	40038	29976	6	29991	80104	200	80111	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	1	1	1	5117	0	0	24	1	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	322	0	1	0	32	25	160100	80100	80084	100	80004	500	640712	40019	40038	40038	29976	6	29991	80104	200	80285	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	2	1	1	1	5117	0	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	321	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	1	1	1	5117	0	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	322	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	1	1	1	5117	0	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	321	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	1	1	1	5117	0	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	310	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	1	1	1	5117	0	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	311	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	40019	40038	40038	29976	6	29991	80104	200	80389	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	1	1	1	5117	0	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	310	0	0	0	32	26	160108	80104	80004	100	80010	500	640066	40025	40045	40046	29973	10	29986	80110	200	80022	200	80022	40045	40046	1	1	80201	100	99	100	80100	100	0	0	0	2	2	2	5127	1	2	23	2	2	40042	80004	80100	40046	40046	40046	40047	40046
80204	40045	310	0	0	0	66	25	160108	80104	80004	100	80010	500	640066	40025	40045	40045	29973	9	29986	80110	200	80022	200	80022	40045	40045	1	1	80201	100	99	100	80100	100	4	0	0	2	2	2	5127	1	2	23	2	2	40042	80004	80100	40047	40046	40047	40047	40046

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	40047	300	0	0	0	0	0	0	2	402	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	7	30066	80091	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	2	3	5020	31	16	13	35	40035	80000	80010	40103	40039	40039	40039	40039
80024	40038	300	0	0	0	0	0	0	0	43	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	17	16	32	32	40035	80000	80010	40039	40039	40039	40039	40039
80025	40038	300	0	0	0	0	48	0	0	1017	25	160010	80010	80000	11	80000	50	640000	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5027	26	16	33	36	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	300	0	0	0	0	0	0	0	43	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	15	16	27	19	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	300	0	0	0	0	0	0	0	43	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5021	30	16	30	31	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	311	0	0	0	0	0	0	0	43	25	160010	80010	80000	10	80000	50	640000	40019	40103	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	1	0	5020	36	16	35	35	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	310	0	0	0	0	0	0	0	107	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	3	5022	33	16	31	29	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	311	0	0	0	0	0	0	0	888	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5022	37	16	35	35	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	310	0	0	0	0	12	0	0	43	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5022	37	16	32	13	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	311	0	0	0	0	0	0	0	43	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5038	30	16	32	33	40035	80000	80010	40039	40039	40039	40039	40039

SMOV (B to W)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations