Firestorm: SMOV (B to X) measurements

Code:

  smov x0, v0.b[1]

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	ac	cf	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	? int output thing (e9)	ec	? int retires (ef)	f5	f6	f7	f8	fd
1004	538	4	0	138	25	2000	1000	1000	1000	8000	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	73	1	16	0	1	1	535	1000	0	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	73	1	16	0	1	1	535	1000	0	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	73	0	16	0	1	1	535	1000	0	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	73	1	16	0	1	1	535	1000	0	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	73	1	16	0	1	1	535	1000	0	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	73	0	16	0	1	1	535	1000	0	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	73	1	16	0	1	1	535	1000	0	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	73	1	16	0	1	1	535	1000	0	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	73	1	16	0	1	1	535	1000	0	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	73	1	16	0	1	1	535	1000	0	1000	539	539	539	539	539

Test 2: Latency 1->2 roundtrip

Code:

  smov x0, v0.b[1]
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	eb	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20204	100038	776	0	0	0	0	0	0	0	1	100023	89565	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	0	100013	100038	100038	96900	3	97496	20100	200	10000	10000	200	10061	10000	100042	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	1	0	0	0	0	1310	1	16	1	1	99637	10000	0	10000	10100	100039	100039	100039	100039	100039
20204	100039	775	0	0	0	0	0	0	0	1	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	0	100013	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	2	0	0	0	0	1310	1	16	1	1	99637	10000	0	10000	10100	100039	100039	100039	100039	100039
20204	100038	775	0	0	0	0	0	0	88	1	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	0	100013	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10002	0	0	0	0	0	0	1310	1	16	1	1	99637	10014	0	10000	10100	100039	100041	100039	100039	100067
20204	100041	776	0	0	0	0	0	0	0	0	100023	89561	25	30100	10100	10000	10000	100	10058	10000	500	4778481	5580349	0	100013	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	2	1	20201	100	99	100	10100	10000	100	0	0	10000	0	2	0	0	0	0	1310	1	16	1	1	99639	10000	0	10000	10100	100041	100039	100039	100039	100042
20204	100038	775	0	0	0	0	0	9	0	0	100023	89599	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	0	100013	100038	100038	96903	3	97497	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10002	0	0	0	0	0	0	1310	1	16	1	1	99637	10000	0	10000	10100	100039	100039	100039	100040	100039
20204	100038	776	0	0	0	0	0	0	0	1	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580406	0	100013	100038	100038	96900	3	97498	20100	200	10000	10000	200	10060	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	3	0	0	1310	1	16	1	1	99637	10000	0	10000	10100	100040	100041	100039	100039	100039
20204	100038	775	0	0	0	0	0	12	0	0	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5657965	1	100308	100038	100038	96901	3	97496	20100	200	10000	10000	204	10240	10255	100393	100420	5	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	2	0	1385	1	16	1	1	99637	10000	0	10000	10100	100039	100042	100039	100039	100039
20204	100038	775	0	0	0	0	0	0	0	0	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580511	0	100017	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100067	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	3	0	0	1310	1	16	2	1	99637	10000	0	10000	10100	100039	100039	100039	100039	100039
20204	100038	775	0	1	0	0	0	0	0	1	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	0	100013	100038	100038	96900	3	97558	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	3	0	0	1310	1	16	1	1	99637	10000	0	10000	10100	100041	100040	100039	100039	100039
20204	100042	776	0	0	0	0	0	0	0	0	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580460	0	100013	100123	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100119	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	1310	1	16	1	1	99638	10000	0	10000	10100	100039	100039	100039	100039	100039

1000 unrolls and 10 iterations

Result (median cycles for code): 10.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20024	100120	776	0	0	0	1	0	237	0	0	100027	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	100014	100038	100038	96922	3	97523	20010	20	10000	10000	20	10000	10000	100038	100039	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	3	0	0	1270	0	18	16	18	18	99637	10000	10000	10010	100119	100039	100039	100039	100039
20024	100041	776	0	1	0	0	0	873	0	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5579064	0	100013	100038	100038	96922	3	97518	20117	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1288	0	18	16	18	18	99641	10000	10000	10010	100039	100039	100039	100039	102643
20024	100038	776	0	0	0	0	0	957	0	0	100023	89564	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5579011	0	100013	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	0	9	16	18	18	99637	10000	10000	10010	100039	100039	100040	100041	100039
20024	100038	775	0	0	0	0	0	492	0	0	100023	89566	100	30040	10019	10008	10006	12	10234	10200	55	4788959	5667808	1	100343	100416	100412	97115	19	97774	20451	20	10303	10242	20	10241	10121	100471	100471	4	1	20021	10	9	10	10010	10000	10	0	0	10000	1	0	0	0	0	1270	0	18	16	10	18	99637	10000	10000	10010	100039	100039	100039	100039	100039
20024	100038	776	0	0	0	0	0	951	0	0	100023	89562	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	100013	100038	100039	96922	3	97518	20010	20	10000	10066	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	5	0	3	0	0	1270	0	18	16	18	18	99637	10003	10000	10010	100039	100039	100039	100039	100041
20024	100038	775	0	0	0	0	0	309	0	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778625	5578954	0	100013	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	1	0	0	0	0	1270	0	18	16	18	8	99637	10000	10000	10010	100039	100039	100039	100039	100039
20024	100038	775	0	0	0	0	0	948	0	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	100013	100038	100041	96925	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	0	15	16	19	19	99637	10000	10000	10010	100039	100039	100039	100039	100039
20024	100038	775	0	0	0	0	0	591	0	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	100013	100038	100038	96926	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	0	18	16	10	18	99637	10000	10000	10010	100124	100039	100039	100039	100039
20024	100038	776	0	0	0	0	0	969	0	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	100013	100038	100038	96922	8	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	1	0	0	0	0	1270	0	18	16	18	18	99639	10003	10000	10010	100039	100039	100039	100039	100039
20024	100038	775	0	1	0	0	0	444	0	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778817	5578954	0	100013	100038	100042	96922	3	97579	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	2	0	10000	1	0	0	0	0	1270	0	18	16	18	10	99637	10000	10000	10010	100039	100130	100039	100039	100039

Test 3: throughput

Count: 8

Code:

  smov x0, v8.b[1]
  smov x1, v8.b[1]
  smov x2, v8.b[1]
  smov x3, v8.b[1]
  smov x4, v8.b[1]
  smov x5, v8.b[1]
  smov x6, v8.b[1]
  smov x7, v8.b[1]

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	40051	311	0	0	0	0	135	0	0	32	25	160100	80100	80000	100	80004	500	640024	0	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	1	0	147	0	1	1	1	5117	0	16	0	1	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	311	0	0	0	0	0	0	0	68	25	160100	80100	80000	100	80004	500	640024	0	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	0	222	0	1	1	1	5117	0	16	0	0	40035	80000	80100	40039	40039	40039	40106	40039
80204	40038	310	0	0	0	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640744	0	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	0	748	0	1	1	1	5117	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	310	0	1	0	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	0	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	0	201	0	1	1	1	5117	0	16	0	0	40035	80000	80100	40039	40039	40107	40039	40039
80204	40038	310	0	0	0	0	132	0	0	32	25	160268	80100	80000	100	80004	500	640024	0	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40168	1	1	80201	100	99	100	80100	100	0	0	0	0	0	165	0	1	1	1	5117	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	310	0	0	0	0	12	0	0	230	25	160100	80100	80000	100	80004	500	640024	0	40019	40106	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	0	189	0	1	1	1	5117	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	310	0	0	0	0	0	0	0	32	25	160100	80100	80000	100	80090	500	640024	0	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	0	192	0	1	1	1	5117	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	311	0	0	0	0	0	0	0	261	25	160100	80100	80000	100	80004	500	640024	0	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	1	0	225	0	1	1	1	5117	0	16	0	0	40035	80000	80100	40039	40039	40107	40039	40039
80204	40038	310	0	0	0	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	1	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	2	1	80201	100	99	100	80100	100	0	0	0	0	0	204	0	1	1	1	5117	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	310	0	0	0	0	0	0	0	42	25	160100	80100	80000	100	80004	500	640024	0	40019	40038	40105	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	0	183	0	1	1	1	5117	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40106

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	40040	299	0	0	0	43	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	5020	3	16	3	3	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	300	0	0	0	43	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	5020	3	16	3	3	40035	80000	80010	40039	40039	40039	40106	40039
80024	40038	299	0	0	0	43	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	237	0	5020	3	16	3	3	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	299	0	0	0	43	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	5020	3	16	3	3	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	300	0	0	0	43	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	5020	3	16	3	3	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	300	0	0	0	43	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	5020	3	16	3	2	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	300	0	0	0	43	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	5020	3	16	2	3	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	299	0	0	12	43	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	5020	3	16	3	3	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	300	0	0	0	43	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	5020	3	16	3	3	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	300	0	0	0	43	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	2	5069	4	32	3	3	40035	80000	80010	40039	40039	40039	40039	40039

SMOV (B to X)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations