Firestorm: SMOV (H to W) measurements

Code:

  smov w0, v0.h[1]

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	538	4	0	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	85	0	16	535	1000	1000	539	539	539	539	539
1004	538	4	0	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	78	0	16	535	1000	1000	539	539	539	539	539
1004	538	5	0	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	76	0	16	535	1000	1000	539	539	539	539	539
1004	538	4	0	0	63	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	76	0	16	535	1000	1000	539	539	539	539	539
1004	538	5	0	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	76	0	16	535	1000	1000	539	539	539	539	539
1004	538	4	0	0	64	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	76	0	16	535	1000	1000	539	539	539	539	539
1004	538	5	0	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	76	0	16	535	1000	1000	539	539	539	539	539
1004	538	4	0	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	76	0	16	535	1000	1000	539	539	539	539	539
1004	538	4	0	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	76	0	16	535	1000	1000	539	539	539	539	539
1004	538	4	0	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	76	0	16	535	1000	1000	539	539	539	539	539

Test 2: Latency 1->2 roundtrip

Code:

  smov w0, v0.h[1]
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	40	49	4c	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20204	100042	776	0	0	0	0	57	0	100023	0	0	0	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778625	5580349	0	5	100013	100038	100038	96903	3	97499	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1310	1	16	1	1	99637	10000	10000	10100	100039	100039	100039	100039	100039
20204	100053	776	0	0	0	0	0	0	100023	0	0	0	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	0	0	100013	100038	100038	96900	3	97496	20100	200	10000	10000	200	10243	10000	100046	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	1	0	3	0	1310	1	16	1	1	99637	10000	10000	10100	100039	100039	100039	100039	100072
20204	100038	776	0	0	0	0	0	0	100023	0	0	0	89564	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	0	0	100013	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1310	1	16	1	1	99637	10000	10000	10100	100039	100039	100039	100039	100039
20204	100038	775	0	0	0	0	0	0	100023	0	0	0	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	0	0	100013	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100040	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	3	0	1310	1	16	1	1	99637	10000	10000	10100	100042	100039	100119	100039	100039
20204	100038	776	0	0	0	0	0	0	100023	0	0	0	89561	45	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	0	0	100013	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1310	1	16	1	1	99637	10000	10000	10100	100039	100039	100039	100039	100039
20204	100038	775	0	1	0	0	0	0	100101	0	0	0	89564	25	30100	10100	10000	10002	100	10000	10000	500	4778481	5580349	0	0	100013	100039	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100118	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	1	0	3	0	1310	1	16	1	1	99637	10000	10000	10100	100039	100039	100039	100039	100039
20204	100038	803	0	0	0	0	0	0	100023	0	0	0	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	0	0	100016	100038	100040	96900	3	97505	20100	200	10000	10000	200	10247	10000	100039	100038	2	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1310	1	16	1	2	99637	10000	10000	10100	100039	100039	100041	100039	100039
20204	100038	804	0	0	0	0	12	0	100023	0	0	0	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580511	0	0	100014	100038	100038	96902	3	97496	20100	200	10000	10000	200	10000	10000	100038	100040	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1310	1	16	1	1	99637	10000	10000	10100	100039	100039	100039	100039	100040
20204	100038	803	0	0	0	0	0	0	100023	0	0	0	89561	25	30100	10108	10000	10000	100	10000	10000	500	4778481	5580349	0	0	100013	100038	100038	96901	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	3	0	1310	1	16	1	1	99637	10000	10000	10100	100039	100040	100039	100039	100039
20204	100038	803	1	0	0	0	132	0	100023	0	0	0	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778625	5580349	0	0	100017	100038	100038	96900	3	97498	20100	200	10000	10000	200	10000	10000	100038	100040	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1310	1	16	1	1	99637	10000	10000	10100	100039	100123	100039	100039	100042

1000 unrolls and 10 iterations

Result (median cycles for code): 10.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	0e	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	91	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20024	100039	776	0	0	0	0	0	0	0	0	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	55	4778481	5578954	100013	100038	100038	96922	3	97520	20010	20	10000	10000	20	10000	10000	100038	100039	1	1	20021	10	9	0	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	2	16	2	2	99637	10000	10000	10010	100039	100039	100039	100039	100039
20024	100038	775	0	0	0	0	0	0	0	0	0	100023	89561	25	30018	10010	10000	10000	10	10000	10000	50	4778481	5578954	100013	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100044	100038	1	1	20021	10	9	0	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	2	16	2	2	99637	10000	10000	10010	100039	100039	100040	100039	100040
20024	101933	776	0	0	0	0	1	0	0	12	0	100023	89561	25	30010	10010	10000	10000	10	10056	10000	50	4778481	5578954	100013	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100118	100038	1	1	20021	10	9	0	10	10010	10000	10	0	0	10000	1	0	3409	0	0	1270	2	24	2	2	99637	10000	10000	10010	100039	100039	100039	100041	100039
20024	100122	776	0	0	0	0	0	1	0	12	0	100023	89561	25	30010	10010	10000	10000	10	10000	10050	50	4778481	5578954	100013	100117	100038	96962	3	97518	20010	20	10000	10000	20	10000	10000	100225	100246	3	1	20021	10	9	1	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	2	16	2	2	99637	10000	10000	10010	100041	100040	100039	100041	100039
20024	100038	776	0	0	0	0	0	1	0	0	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	55	4778481	5578954	100013	100038	100119	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100122	1	1	20021	10	9	0	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	3	16	7	2	99637	10000	10000	10010	100039	100039	100039	100039	100041
20024	100038	775	0	0	0	0	0	0	0	12	0	100023	89562	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5579119	100013	100038	100038	96962	3	97519	20010	20	10000	10000	20	10000	10000	100038	100040	1	1	20021	10	9	0	10	10010	10000	10	0	0	10000	0	0	3	0	0	1270	3	16	2	2	99926	10000	10000	10010	100039	100040	100039	100039	100039
20024	100038	776	0	0	0	0	0	0	0	12	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5582376	100013	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	0	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	2	16	2	3	99637	10000	10000	10010	100039	100039	100040	100039	100039
20024	100038	775	0	0	0	0	0	0	0	0	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5579009	100013	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100040	100038	1	1	20021	10	9	0	10	10010	10000	10	0	0	10000	0	0	3	0	0	1270	4	16	2	2	99637	10000	10000	10010	100039	100039	100039	100039	100039
20024	100038	776	0	0	0	0	0	0	0	0	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	100015	100038	100038	96922	7	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	0	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	2	16	2	2	99637	10000	10000	10010	100039	100039	100039	100039	100039
20024	100038	776	0	0	0	0	0	0	0	132	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	100013	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	0	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	3	16	2	2	99637	10000	10000	10010	100041	100039	100039	100040	100039

Test 3: throughput

Count: 8

Code:

  smov w0, v8.h[1]
  smov w1, v8.h[1]
  smov w2, v8.h[1]
  smov w3, v8.h[1]
  smov w4, v8.h[1]
  smov w5, v8.h[1]
  smov w6, v8.h[1]
  smov w7, v8.h[1]

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	91	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	40052	322	0	0	0	0	0	0	60	25	160100	80100	80000	100	80004	500	640024	1	40019	40038	40038	29976	6	29991	80104	200	80104	200	80016	40038	40038	1	1	80201	100	99	0	100	80100	100	0	0	0	0	1	1	1	5117	0	16	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	322	0	0	1	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	0	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40469	1	1	80201	100	99	0	100	80100	100	0	0	1	3	1	1	1	5117	0	16	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	322	0	0	0	0	0	0	88	25	160100	80100	80000	100	80004	500	640024	0	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	0	100	80100	100	0	9	1	3	1	1	1	5117	0	16	0	40035	80000	80100	40039	40039	40314	40313	40454
80204	40038	321	0	0	0	1	0	0	32	25	160100	80100	80086	100	80004	500	640718	0	40019	40038	40038	29976	11	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	0	100	80100	100	0	0	0	558	1	1	1	5117	1	16	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40105	321	0	0	1	0	0	88	32	25	160272	80100	80000	100	80004	500	640024	0	40019	40038	40038	29976	6	30036	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	0	100	80100	100	0	0	0	3	1	1	1	5117	1	16	0	40035	80000	80100	40107	40039	40039	40039	40039
80204	40038	322	0	0	0	0	132	0	32	44	160100	80100	80000	100	80004	500	640024	1	40019	40038	40038	29976	6	30037	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	0	100	80100	100	0	0	1	0	1	1	1	5117	0	16	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	321	0	0	0	0	132	0	32	46	160100	80100	80000	100	80004	500	640024	1	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	0	100	80100	100	0	0	0	0	1	1	1	5117	1	16	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	321	0	0	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	0	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	0	100	80100	100	0	0	0	0	1	1	1	5117	0	16	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	321	0	0	0	0	0	0	60	25	160100	80100	80000	100	80004	500	640712	0	40019	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	0	100	80100	100	0	0	0	0	1	1	1	5117	0	16	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	321	0	0	0	0	12	0	74	45	160100	80100	80000	100	80004	500	640024	0	40019	40038	40038	29976	6	29991	80104	200	80016	200	80104	40038	40038	1	1	80201	100	99	0	100	80100	100	0	0	0	0	1	1	1	5117	0	16	0	40035	80000	80100	40039	40039	40039	40039	40039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss instruction (0a)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	l1d tlb miss nonspec (c1)	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80024	40048	300	0	0	0	0	0	0	43	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	9	16	8	9	40954	80000	80010	40039	40631	40369	40039	40039
80024	41400	312	1	1	25	27	3432	2200	481	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	2	21	0	2	5020	8	16	8	8	40035	80319	80010	40039	40039	40039	40039	40105
80024	40038	313	1	0	0	4	33	0	43	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	8	16	8	9	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	313	0	0	0	0	15	0	71	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	8	16	8	10	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	310	0	0	0	0	9	0	43	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40103	40038	2	1	80021	10	9	10	80010	10	3	0	11	0	5020	10	16	9	5	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	300	0	0	0	0	0	0	708	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	114	0	0	5020	8	16	9	8	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	300	0	0	0	0	0	0	43	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	10	16	10	9	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	300	0	0	0	0	0	0	43	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	8	16	8	8	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	300	0	0	0	0	0	0	43	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	5020	8	16	10	6	40035	80000	80010	40039	40039	40039	40039	40039
80024	40038	300	0	0	0	0	0	0	43	25	160010	80010	80000	10	80000	50	640000	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	5088	8	16	8	9	40035	80000	80010	40039	40039	40039	40039	40039

SMOV (H to W)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations