Firestorm: SMOV (H to X) measurements

Code:

  smov x0, v0.h[1]

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	538	4	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	1	16	0	1	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	1	16	0	1	535	1000	1000	539	539	539	539	539
1004	538	5	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	1	16	1	0	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	1	16	1	0	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	6	73	0	16	2	1	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	2	16	2	2	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	1	16	1	1	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	0	16	1	1	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	1	16	0	1	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	0	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	1	16	1	1	535	1000	1000	539	539	539	539	539

Test 2: Latency 1->2 roundtrip

Code:

  smov x0, v0.h[1]
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20204	100038	776	0	0	0	0	0	0	0	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	0	100013	100071	100044	96900	12	97562	20100	200	10000	10000	200	10000	10000	100038	100040	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1331	1	16	1	1	99637	10000	0	10000	10100	100042	100039	100039	100039	100039
20204	100038	775	0	0	0	0	0	0	0	100028	89565	25	30100	10100	10002	10000	100	10000	10000	500	4778529	5580349	0	100013	100067	100040	96900	3	97496	20100	200	10000	10000	202	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	3305	0	1310	1	25	1	1	99637	10000	0	10000	10100	100039	100039	100039	100039	100040
20204	100038	776	0	0	0	1	0	0	0	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4781157	5580349	0	100015	100084	100042	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1354	1	16	1	1	99637	10000	0	10000	10100	100039	100040	100039	100039	100041
20204	100038	775	0	0	0	0	0	0	0	100023	89561	45	30100	10104	10000	10002	100	10115	10000	538	4778481	5588855	0	100013	100077	100042	96900	10	97549	20224	202	10123	10124	204	10061	10124	100203	100211	2	1	20201	100	99	100	10100	10000	100	4	2	10004	0	0	0	6645	2	1310	2	16	1	1	99637	10026	0	10000	10100	100120	100039	100039	100805	100039
20204	100038	776	0	1	1	0	1	0	176	100188	89602	63	30100	10121	10000	10000	100	10000	10000	500	4778481	5580349	0	100014	100038	100039	96901	3	97496	20100	200	10000	10000	200	10000	10000	100038	100039	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	1	0	0	0	1310	1	16	1	1	99637	10000	0	10000	10100	100039	100039	100039	100039	100039
20204	100038	775	0	0	0	0	0	0	0	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	0	100013	100041	100038	96904	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	3	0	1310	1	16	1	1	99637	10000	0	10000	10100	100039	100039	100039	100039	100041
20204	100038	776	0	0	0	0	0	0	0	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	0	100013	100048	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	3	0	1310	1	16	1	1	99637	10000	0	10000	10100	100042	100039	100039	100039	100039
20204	100041	775	0	0	0	0	0	12	0	100024	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778529	5580349	0	100013	100039	100041	96903	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	1	0	0	0	1310	1	16	1	1	99728	10000	1	10000	10100	100041	100039	100039	100039	100039
20204	100038	775	0	0	0	0	0	12	0	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	1	100014	100065	100050	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	3	0	1310	1	16	1	1	99637	10000	0	10000	10100	100039	100039	100039	100039	100039
20204	100038	776	0	0	0	0	0	0	0	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	0	100013	100064	100042	96900	3	97496	20100	200	10000	10067	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	1	0	0	0	1310	1	16	1	1	99637	10000	0	10000	10100	100039	100039	100041	100039	100039

1000 unrolls and 10 iterations

Result (median cycles for code): 10.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0e	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20024	100038	775	0	0	0	0	0	0	0	100071	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	100019	100038	100038	96922	3	97518	20010	20	10000	10000	20	10060	10121	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	10004	0	0	0	0	0	0	1270	2	16	2	2	99637	10000	10000	10010	100039	100039	100039	100039	100039
20024	100040	776	0	0	0	0	0	0	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	100013	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	1	0	0	0	0	1270	2	24	3	2	99640	10000	10000	10010	100039	100039	100039	100039	100039
20024	100075	775	0	0	0	1	0	0	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778577	5578954	0	100013	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100041	2	1	20021	10	9	10	10010	10000	10	0	10000	0	1	0	0	0	0	1270	2	16	3	2	99638	10000	10000	10010	100039	100039	100039	100039	100039
20024	100038	775	0	0	0	0	0	0	0	100026	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	100013	100038	100038	96922	3	97519	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	0	1270	3	16	2	2	99637	10000	10000	10010	100041	100207	102695	101659	100039
20024	100038	775	0	0	0	0	0	0	0	100024	89603	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	100013	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100039	100039	1	1	20021	10	9	10	10010	10000	10	0	10000	0	1	0	0	0	0	1270	2	16	2	2	99640	10000	10000	10010	100039	100039	100039	100039	100039
20024	100038	775	0	0	0	0	0	0	0	100023	89561	25	30019	10010	10000	10000	10	10000	10000	50	4778529	5578954	0	100013	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	0	1270	3	16	2	3	99637	10000	10000	10010	100039	100039	100039	100039	100123
20024	100038	807	0	0	0	0	0	0	0	100106	89561	25	30010	10010	10002	10000	10	10000	10000	50	4778481	5578954	0	100013	100038	100038	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100039	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	3	0	0	1270	2	16	2	2	99637	10000	10000	10010	100039	100040	100039	100039	100039
20024	100041	775	0	0	0	0	0	0	0	100024	89561	25	30010	10010	10000	10000	10	10057	10000	50	4778577	5578954	0	100013	100038	100039	96922	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	1	0	0	0	0	1270	2	16	2	2	99637	10000	10000	10010	100039	100039	100039	100039	100039
20024	100038	775	0	0	0	0	0	12	0	100024	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	100013	100038	100040	96922	3	97518	20118	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	3	0	0	1288	2	16	2	2	99637	10000	10000	10010	100039	100039	100039	100039	100039
20024	100039	776	0	0	0	0	0	0	0	100025	89561	25	30017	10010	10000	10000	10	10000	10000	50	4778481	5578954	1	100013	100038	100038	96927	3	97520	20010	20	10061	10000	20	10000	10000	100038	100040	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	0	1270	2	16	2	3	99637	10000	10000	10010	100039	100039	100039	100039	100124

Test 3: throughput

Count: 8

Code:

  smov x0, v8.h[1]
  smov x1, v8.h[1]
  smov x2, v8.h[1]
  smov x3, v8.h[1]
  smov x4, v8.h[1]
  smov x5, v8.h[1]
  smov x6, v8.h[1]
  smov x7, v8.h[1]

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	40038	322	0	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	40019	0	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	1	1	1	5117	0	0	16	0	0	40035	80000	80100	40039	40039	40105	40039	40039
80204	40038	322	0	0	0	0	0	32	25	160100	80100	80088	100	80004	500	640760	40075	0	40038	40038	29976	6	30038	80104	200	80016	200	80016	40038	40038	2	1	80201	100	99	100	80100	100	0	0	0	0	0	0	1	1	1	5117	0	0	24	0	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	322	0	0	0	0	0	32	81	160272	80186	80000	100	80004	500	640024	40019	0	40038	40105	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	2	0	0	0	585	1	1	1	5117	0	1	16	0	0	40035	80000	80100	40039	40039	40039	40106	40039
80204	40038	322	0	0	0	0	27	245	43	160100	80100	80000	100	80004	500	640712	40019	0	40106	40038	29976	6	30036	80104	200	80118	200	80016	40313	40109	2	1	80201	100	99	100	80100	100	2	0	0	0	0	0	1	1	1	5117	0	0	24	0	0	40035	80082	80100	40039	40039	40039	40039	40108
80204	40038	321	0	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	40019	0	40038	40038	29976	6	29991	80196	200	80016	200	80111	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	0	570	1	1	1	5117	0	0	16	0	0	40035	80000	80100	40039	40039	40039	40109	40039
80204	40038	321	0	0	0	1	0	32	25	160264	80100	80000	100	80004	500	640024	40019	0	40038	40038	29976	12	29991	80278	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	1	1	1	5117	0	0	16	0	0	40094	80000	80100	40039	40039	40039	40039	40108
80204	40038	322	0	0	0	0	0	32	25	160100	80186	80000	100	80004	500	640024	40019	0	40038	40038	29976	6	30038	80104	200	80016	200	80016	40038	40038	2	1	80201	100	99	100	80100	100	0	0	0	0	0	0	1	1	1	5117	0	0	16	0	0	40035	80000	80100	40039	40106	40039	40039	40105
80204	40038	322	0	0	0	0	0	32	25	160100	80184	80000	100	80004	500	640024	40019	0	40038	40038	30007	6	30037	80104	200	80016	200	80016	40038	40038	2	1	80201	100	99	100	80100	100	0	0	0	0	0	0	1	1	1	5117	0	0	16	0	0	40091	80000	80100	40104	40039	40039	40039	40039
80204	40038	321	0	0	0	0	0	32	25	160100	80100	80000	100	80004	500	640024	40019	0	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	1	1	1	5117	0	0	16	0	0	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	321	0	0	0	0	0	116	25	160100	80100	80000	100	80004	500	640024	40019	0	40038	40038	29976	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	1	1	1	5117	0	0	16	0	0	40035	80000	80100	40107	40107	40238	40109	40106

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d2	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? int retires (ef)	f5	f6	f7	f8	fd
80024	40051	310	0	0	0	43	25	160010	80010	80000	10	80000	50	640000	0	40019	40038	40038	29992	3	30018	80010	20	80088	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	5	16	0	4	4	40035	80000	0	80010	40039	40039	40039	40039	40039
80024	40105	311	1	24	88	43	25	160164	80010	80000	10	80000	50	640000	0	40019	40038	40103	29992	3	30018	80010	20	80000	20	80000	40038	40038	2	1	80021	10	9	10	80010	10	0	0	0	0	90	5020	0	3	16	0	4	4	40035	80000	0	80010	40039	40039	40106	40039	40039
80024	40038	310	0	9	0	233	25	160010	80010	80000	10	80000	50	640000	1	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	102	5037	0	4	24	0	3	5	40035	80000	0	80010	40039	40039	40039	40039	40039
80024	40038	310	0	132	0	43	25	160010	80010	80000	10	80083	50	640000	1	40019	40038	40038	29992	3	30018	80010	20	80000	20	80089	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	569	5037	0	4	16	0	4	4	40035	80000	0	80010	40171	40104	40039	40039	40039
80024	40104	310	0	0	88	43	43	160010	80010	80000	10	80086	50	640000	1	40019	40104	40038	29992	3	30018	80010	20	80000	20	80000	40103	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	15	5020	0	4	16	0	4	4	40035	80000	0	80010	40039	40039	40039	40039	40039
80024	40038	311	1	0	0	43	25	160168	80010	80000	10	80000	50	640000	0	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	168	5020	0	3	16	0	5	5	40035	80000	0	80010	40039	40039	40039	40039	40039
80024	40038	311	0	0	0	43	25	160010	80010	80000	10	80000	50	640000	1	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	108	5020	0	4	16	0	4	4	40035	80000	0	80010	40039	40039	40039	40039	40039
80024	40038	311	0	0	0	43	25	160010	80010	80000	10	80000	50	640000	1	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	159	5020	0	4	16	0	4	4	40035	80000	0	80010	40039	40039	40039	40039	40039
80024	40038	311	0	0	88	53	25	160166	80010	80000	10	80081	50	640000	1	40019	40038	40038	29992	3	30066	80010	20	80089	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	33	5020	0	4	16	0	4	3	40035	80000	0	80010	40104	40039	40313	40039	40660
80024	40038	321	0	0	0	43	25	160010	80010	80000	10	80000	50	640000	1	40019	40104	40038	29992	3	30018	80010	20	80000	20	80000	40038	40104	1	1	80021	10	9	10	80010	10	2	0	0	0	147	5020	0	3	16	0	4	3	40035	80079	0	80010	40039	40039	40039	40039	40039

SMOV (H to X)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations