Firestorm: SMOV (S to X) measurements

Code:

  smov x0, v0.s[1]

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	map dispatch bubble (d6)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
1004	538	5	0	43	25	2000	1000	1000	1000	8000	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	16	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	16	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	16	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	3	73	16	535	1000	1000	539	539	539	539	539
1004	538	5	57	43	25	2000	1000	1000	1000	8000	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	16	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	16	535	1000	1000	539	539	539	539	539
1004	538	5	0	43	25	2000	1000	1000	1000	8000	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	16	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	16	535	1000	1000	539	539	539	539	539
1004	538	4	0	43	25	2000	1000	1000	1000	8000	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	16	535	1000	1000	539	539	539	539	539
1004	538	4	0	85	25	2000	1000	1000	1000	8000	519	538	538	370	3	396	1000	1000	1000	538	538	1	1	1001	1000	0	0	73	16	535	1000	1000	539	539	539	539	539

Test 2: Latency 1->2 roundtrip

Code:

  smov x0, v0.s[1]
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 10.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20204	100041	804	0	0	0	0	6	0	100023	89562	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580461	100088	100039	100038	96900	3	97497	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	1	0	111	0	0	1338	1	16	1	1	99773	10014	10000	10100	100121	100293	100040	100124	100039
20204	100141	804	0	0	1	0	147	0	100227	89639	45	30119	10123	10005	10005	124	10056	10050	597	4783343	5667565	100170	100212	100203	96997	13	97621	20567	206	10060	10123	200	10246	10060	100287	100122	4	1	20201	100	99	100	10100	10000	100	7	2	10002	0	0	3530	0	0	1329	1	33	1	2	99858	10004	10000	10100	100040	100039	100039	100039	100042
20204	100062	804	0	0	0	0	15	0	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	100013	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	150	0	0	1310	1	16	1	1	99638	10000	10000	10100	100039	100039	100039	100039	100042
20204	100094	804	0	0	0	0	3	0	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	100013	100040	100038	96901	3	97496	20100	200	10000	10000	200	10000	10000	100042	100039	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	30	0	0	1310	1	16	1	1	99637	10000	10000	10100	100039	100041	100039	100042	100039
20204	100060	803	0	0	0	0	3	0	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778529	5580349	100013	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	1	0	396	0	0	1310	1	16	1	1	99637	10000	10000	10100	100039	100040	100039	100040	100039
20204	100099	804	0	0	0	0	15	0	100024	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	100013	100038	100039	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100039	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	297	0	0	1310	1	16	1	1	99637	10000	10000	10100	100039	100039	100039	100039	100039
20204	100119	803	0	0	0	0	3	0	100322	89729	104	30157	10131	10010	10008	128	10237	10200	586	4791249	5667258	100013	100038	100117	96900	21	97777	20561	206	10183	10186	204	10000	10059	100042	100040	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	117	0	0	1310	1	16	1	1	99637	10000	10000	10100	100039	100039	100039	100040	100040
20204	100069	804	0	0	0	0	15	0	100023	89561	25	30100	10100	10000	10000	100	10000	10000	500	4778481	5580349	100013	100038	100038	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100039	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	288	0	0	1310	1	16	1	1	99637	10000	10000	10100	100039	100039	100039	100039	100041
20204	100103	804	0	0	0	0	15	0	100023	89561	25	30100	10100	10000	10000	100	10059	10000	500	4778577	5580349	100013	100038	100040	96900	3	97496	20100	200	10000	10000	200	10000	10000	100038	100039	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	273	0	0	1310	1	16	1	1	99637	10000	10000	10100	100039	100039	100039	100039	100040
20204	100087	803	0	0	0	0	0	88	100023	89606	25	30100	10126	10000	10000	120	10000	10000	557	4778481	5580349	100013	100038	100155	96900	3	97496	20100	200	10000	10059	200	10000	10059	100038	100038	1	1	20201	100	99	100	10100	10000	100	0	0	10002	0	2	3564	0	0	1310	1	25	1	1	99712	10000	10000	10100	100039	100039	100120	100039	100127

1000 unrolls and 10 iterations

Result (median cycles for code): 10.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)	f5	f6	f7	f8	fd
20024	100045	776	0	0	0	0	0	303	0	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	100026	100038	100038	97010	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	3	0	1270	1	16	1	1	99637	10000	10000	10010	100039	100039	100039	100039	100039
20024	100041	775	0	0	0	0	0	51	0	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778673	5579009	0	100013	100038	100038	96922	8	97521	20010	20	10000	10066	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	18	0	1270	1	16	1	1	99637	10000	10000	10010	100039	100039	100041	100039	100039
20024	100038	775	0	0	0	0	0	9	0	0	100027	89598	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	100013	100039	100038	97000	3	97518	20010	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10004	0	0	0	0	1270	1	16	1	1	99638	10000	10000	10010	100039	100039	100041	100039	100039
20024	100038	775	0	0	0	0	0	0	0	0	100108	89561	25	30010	10010	10002	10000	10	10000	10000	50	4778481	5579065	1	100013	100066	100095	97017	3	97518	20010	20	10000	10000	20	10066	10000	100042	100119	2	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	1270	1	16	1	1	99637	10000	10000	10010	100040	100039	100039	100039	100041
20025	100095	776	0	0	0	0	0	132	0	0	100023	89561	25	30018	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	100013	100038	100038	96999	3	97518	20010	20	10000	10000	20	10000	10066	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	1270	1	16	1	1	99637	10000	10000	10010	100039	100122	100039	100039	100039
20024	100041	776	0	0	0	0	0	54	0	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	100013	100038	100038	96953	3	97520	20119	20	10000	10000	20	10000	10000	100038	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	1270	1	16	1	1	99637	10000	10000	10010	100043	100039	100039	100039	100039
20024	100038	775	0	0	0	0	0	0	0	0	100027	89561	45	30010	10010	10000	10000	10	10000	10000	50	4778481	5579064	0	100013	100038	100038	96993	3	97521	20010	20	10000	10000	20	10000	10000	100038	100039	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	1270	1	16	1	1	99637	10003	10000	10010	100039	100039	100039	100044	100039
20024	100038	803	0	0	0	0	0	3	0	0	100023	89561	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5601679	0	100013	100038	100038	96924	3	97518	20010	20	10000	10000	20	10000	10000	100038	100042	1	1	20021	10	9	10	10010	10000	10	0	0	10000	1	0	3	0	1270	1	16	1	1	99637	10000	10000	10010	100130	100039	100039	100042	100039
20024	100038	775	0	0	0	0	0	0	0	0	100023	89610	25	30010	10010	10000	10000	10	10000	10000	50	4778481	5578954	0	100013	100038	100038	96950	3	97518	20010	20	10121	10000	20	10000	10000	100038	100040	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	3	0	1270	1	16	1	1	99637	10000	10000	10010	100039	100039	100039	100039	100039
20024	100038	775	0	0	0	0	0	0	0	0	100023	89561	25	30010	10010	10000	10000	10	10059	10000	50	4778481	5579064	0	100013	100038	100108	96923	3	97518	20010	20	10000	10000	20	10000	10000	100045	100038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	1270	1	16	1	1	99637	10000	10000	10010	100039	100042	100039	100039	100039

Test 3: throughput

Count: 8

Code:

  smov x0, v8.s[1]
  smov x1, v8.s[1]
  smov x2, v8.s[1]
  smov x3, v8.s[1]
  smov x4, v8.s[1]
  smov x5, v8.s[1]
  smov x6, v8.s[1]
  smov x7, v8.s[1]

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	l1i cache miss demand (d3)	map dispatch bubble (d6)	e0	? int output thing (e9)	? int retires (ef)	f5	f6	f7	f8	fd
80204	40050	310	1	0	47	25	160100	80100	80000	100	80096	500	640024	40019	40317	40038	29976	0	6	29991	80104	200	80285	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	1	3	1	1	1	5117	0	16	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	300	0	0	32	25	160100	80100	80000	100	80004	500	640024	40019	40038	40038	29976	0	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	0	16	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	300	0	0	32	25	160100	80100	80000	100	80004	500	640718	40019	40038	40038	29976	0	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	13	24	1	1	1	5117	0	16	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	300	0	0	32	25	160100	80100	80000	100	80004	500	640024	40019	40038	40038	29976	0	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	0	16	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	300	0	0	32	25	160100	80100	80000	100	80004	500	640024	40019	40038	40038	30004	0	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	0	16	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	300	0	0	32	25	160100	80100	80000	100	80004	500	640024	40019	40038	40038	29976	0	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	0	16	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	300	0	0	32	25	160100	80100	80000	100	80004	500	640024	40019	40038	40038	29976	0	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	0	16	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	300	0	0	32	25	160100	80100	80000	100	80004	500	640744	40019	40038	40038	29976	0	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	0	16	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	300	0	0	32	25	160100	80100	80000	100	80004	500	640024	40019	40038	40038	29976	0	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	0	16	40035	80000	80100	40039	40039	40039	40039	40039
80204	40038	300	0	0	697	25	160100	80100	80000	100	80004	500	640024	40019	40038	40038	29976	0	6	29991	80104	200	80016	200	80016	40038	40038	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	0	16	40035	80000	80100	40039	40039	40039	40039	40039

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	18	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d2	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? int output thing (e9)	ec	? int retires (ef)	f5	f6	f7	f8	fd
80024	40048	310	0	0	0	12	0	68	25	160010	80010	80000	10	80000	50	640000	0	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5020	0	31	17	0	32	29	40035	80000	0	80010	40039	40039	40039	40039	40039
80024	40038	310	0	0	0	15	0	43	25	160010	80010	80000	10	80000	50	640000	0	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5020	0	31	16	0	15	33	40035	80000	0	80010	40039	40039	40039	40039	40039
80024	40038	310	0	0	0	9	0	43	25	160010	80010	80000	10	80000	50	640000	0	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5020	0	32	16	0	35	18	40035	80000	0	80010	40039	40039	40039	40039	40039
80024	40038	310	1	0	0	0	0	43	61	160176	80087	80000	10	80000	50	640000	0	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5020	0	30	16	0	30	33	40035	80000	0	80010	40039	40039	40039	40039	40039
80024	40038	310	0	0	0	0	0	43	25	160010	80010	80000	10	80000	50	640000	0	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5020	0	31	16	0	16	33	40035	80000	0	80010	40039	40039	40039	40039	40039
80024	40038	310	0	0	0	0	0	183	25	160010	80010	80000	10	80000	50	640000	0	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5020	0	33	16	0	31	31	40035	80000	0	80010	40039	40039	40039	40130	40039
80024	40038	310	0	0	0	0	0	43	25	160010	80010	80000	10	80000	50	640000	0	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5020	0	34	16	0	33	17	40035	80000	0	80010	40039	40039	40039	40039	40039
80024	40038	311	0	0	0	0	0	423	25	160010	80010	80000	10	80000	50	640000	0	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5020	0	32	16	0	16	38	40035	80000	0	80010	40039	40039	40039	40039	40039
80024	40038	310	0	0	0	0	0	43	25	160010	80010	80000	10	80000	50	640000	0	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5020	0	30	16	0	35	35	40035	80000	0	80010	40039	40039	40039	40039	40039
80024	40038	310	0	0	0	0	0	43	25	160010	80010	80000	10	80000	50	640000	0	40019	40038	40038	29992	3	30018	80010	20	80000	20	80000	40038	40038	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5020	0	31	16	0	36	35	40035	80000	0	80010	40039	40039	40039	40039	40039

SMOV (S to X)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations