Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SMULL2 (by element, 2D)

Test 1: uops

Code:

  smull2 v0.2d, v0.4s, v1.s[1]
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037230612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037220612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230822548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037220612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230822548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230612548251000100010003983133018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230612548251000100010003983133018303730372415328951000100020003037303711100110001073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  smull2 v0.2d, v0.4s, v1.s[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0318191e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722400285061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225000061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372250000549295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372250015061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372250030061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372250015061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
1020430037225006161295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
102043003722500150251295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372250015061295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001000007101161129634100001003003830038300383003830038
10204300372250057061295482510100100100161001000050042773131300183003730037282653287451010020010000200203323013230037111020110099100100100001001607102241229634100001003003830038300383008530038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037224000000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
1002430037225000060612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
1002430037225000060662954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
10024300372250000180612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
10024300372250000540612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
10024300372240000180612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
1002430037225000060612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
1002430037225000060612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
10024300372250000360612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038
10024300372250000360612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000006402162229630010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  smull2 v0.2d, v1.4s, v0.s[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722501861295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000027102162229634100001003003830038300383003830038
1020430037225039536295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000007102162229634100001003003830038300383003830038
102043003722500346295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000007102162229634100001003003830038300383003830038
102043003722500631295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000007102162229634100001003003830038300383003830038
102043003722500726295482510100100100001001000050042773130300183003730037282653287451010020010000200200003003730037111020110099100100100001003007102162229634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000007102162229634100001003003830038300383003830038
102043003722502161295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000007102162229634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000007102162229634100001003003830038300383003830038
10204300372250061295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000007102162229634100001003003830038300383003830038
102043003722500536295482510100100100001001000050042773131300183003730037282653287451010020010000200200003003730037111020110099100100100001000007102162229634100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500612954825100101010000101000050427731303002030037300372828732876710010201000020200003003730037111002110910101000010000000640316332963010000103003830038300383003830038
100243003722400612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000640316332963010000103003830038300383003830038
100243003722400612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000001640316332963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000640316332963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000640316332963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000640316332963010000103003830038300383003830038
100243003722400612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000640316332963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000640316332963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000640316332963010000103003830038300383003830038
100243003722500612954825100101010000101000050427731303001830037300372828732879010010201000020200003003730037111002110910101000010000000640316332963010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  smull2 v0.2d, v8.4s, v9.s[1]
  smull2 v1.2d, v8.4s, v9.s[1]
  smull2 v2.2d, v8.4s, v9.s[1]
  smull2 v3.2d, v8.4s, v9.s[1]
  smull2 v4.2d, v8.4s, v9.s[1]
  smull2 v5.2d, v8.4s, v9.s[1]
  smull2 v6.2d, v8.4s, v9.s[1]
  smull2 v7.2d, v8.4s, v9.s[1]
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9faccfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420058150042412580100100800001008000050064000002002020039200399973399978010020080000200160000200392003911802011009910010080000100051102161120036800001002004020040200402004020040
8020420039150001572580100100800001008000050064000002002020039200399973399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040
802042003915000412580100100800001008000050064000002002020039200399973399978010020080105200160000200392003911802011009910010080000100051101161120333800001002004020040200402004020118
8020420039150021412580100100800001008000050064000002002020039200399973399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040
8020420039150015412580100100800001008000050064082002002020039200399973399978010020080000200160000200392003921802011009910010080000100051101161120036800001002004020040200402004020040
8020420039150015412580100100800001008000050064000002002020039200399973399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040
8020420039150012412580100100800001008000050064000002002020039200399973399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040
802042003915000412580100100800001008000050064000002002020039200399973399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040
802042003915000412580206100800001008000050064000002002020039200399973399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040
802042003915000412580100100800001008000050064000002002020039200399973399978010020080000200160000200392003911802011009910010080000100051101161120036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420039150244025800101080000108000050640000200200200392003999963100198001020800002016000020039200391180021109101080000100005020616242003680000102004020040200402004020040
800242003915004025800101080000108000050640000200200200392003999963100198001020800002016000020039200391180021109101080000100005020416422003680000102004020040200402004020040
80024200391501954025801111080000108000050640000200200200392003999963100198001020800002016000020039200391180021109101080000100005020216422003680000102004020040200402004020040
800242003915004025800101080000108000050640000200200200392003999963100198001020800002016000020039200391180021109101080000100005020416422003680000102004020040200402004020040
800242003915034025800101080000108000050640000200200200392003999963100198001020800002016000020039200391180021109101080000100005020416242003680000102004020040200402004020040
800242003915004025800101080000108000050640000200200200392003999963100198001020800002016000020039200391180021109101080000100005020416242003680000102004020040200402004020040
800242003915004025800101080000108000050640000200200200392003999963100198001020800002016000020039200391180021109101080000100005020216422003680000102004020040200402004020040
80024200391503034025800101080000108000050640000200200200392003999963100198001020800002016000020039200391180021109101080000100005020416242003680000102004020040200402004020040
80024200391502854025800101080000108000050640000200200200392003999963100198001020800002016000020039200391180021109101080000100005020216242003680000102004020040200402004020040
800242003915004025800101080000108000050640000200200200392003999963100198001020800002016000020039200391180021109101080000100005020416242003680000102004020040200402004020040