Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SMULL2 (by element, 4S)

Test 1: uops

Code:

  smull2 v0.4s, v0.8h, v1.h[1]
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037230061254825100010001000398313030183037303724153289510001000200030373037111001100012773116112630100030383038303830383038
10043037230061254825100010001000398313030183037303724153289510001000200030373037111001100010073116112630100030383038303830383038
1004303723106125482510001008100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
10043037230010525482510001000100039831313018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
1004303723006125482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372200612548251000100010003983131301830373037241532895100010002000303730371110011000012373116112630100030383038303830383038
1004303723007925482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038
100430372200822548251000100010003983130301830373037241532895100010002000303730371110011000010573116112630100030383038303830383038
1004303722006125482510001000100039831313018303730372415328951000100020003037303711100110000373116112630100030383038303830383038
10043037230015625482510001000100039831303018303730372415328951000100020003037303711100110000073116112630100030383038303830383038

Test 2: Latency 1->2

Code:

  smull2 v0.4s, v0.8h, v1.h[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0309l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372250002082954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372250001052954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
1020430037224000612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
1020430037224000612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
1020430037225000612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372250001262954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372250001892954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
10204300372250001452954825101001001000012810149587427859803001830037300372826582876310100200100002002000030037300371110201100991001001000010020073311611296348100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250000009152954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000006403163329630010000103003830038300383003830038
10024300372250000001262954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000006403163329630010000103003830038300383003830038
10024300372250000001262954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000006403163329630010000103003830038300383003830038
1002430037225000000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000006403163329630010000103003830038300383003830038
1002430037225000000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000006403163329630010000103003830038300383003830038
1002430037225000000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000006403163329630010000103003830038300383003830038
1002430037225000000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000006403163329630010000103003830038300383003830038
1002430084225000000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000006403163329630010000103003830038300383003830038
1002430037225000000612954825100101010000101000050427731313001830037300372828732876710010201000020200003003730037111002110910101000010000000006403163329630010000103003830038300383003830038
1002430037225000000612954825100101010000101000050427731303001830037300372828732876710010201000020200003003730037111002110910101000010000000006403163329630010000103003830038300383003830038

Test 3: Latency 1->3

Code:

  smull2 v0.4s, v1.8h, v0.h[1]
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037224002122954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071021611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
1020430037225002242954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731313001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
1020430037225006129548251010010010000100100005004277313030018300373003728265328745101002001000020020000300373003711102011009910010010000100001271011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010000500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038
102043003722500612954825101001001000010010149500427731303001830037300372826532874510100200100002002000030037300371110201100991001001000010000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0318191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250000147295482510010101000010100005042773131300183003730037282873287671001020100002020000300373003711100211091010100001000006403163429630010000103003830038300383003830038
100243003722500001032954825100101010000101000050427731303001830037300372828712287671001020100002020000300373003731100211091010100001000006403163329630010000103003830038300383003830038
1002430037225000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000006403163429630010000103003830038300383003830038
1002430037225000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000006403163329630010000103003830038300383003830038
1002430037225001560356295302510010101000010100005042786701300183003730037282873287671001020100002020000300373003711100211091010100001001006403163329668010000103003830038300383003830085
10024300842250000685295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000006403163329630010000103003830038300383003830038
1002430037225000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000006403163329630010000103003830038300383003830038
10024300372250012061295482510010121000812100005042773131300183003730037282873287671001020100002220000300373003711100211091010100001020006403163329630010000103003830038300383003830038
1002430037225000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000006403163329630010000103003830038300383003830038
1002430037224000061295482510010101000010100005042773130300183003730037282873287671001020100002020000300373003711100211091010100001000006403163429630010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  smull2 v0.4s, v8.8h, v9.h[1]
  smull2 v1.4s, v8.8h, v9.h[1]
  smull2 v2.4s, v8.8h, v9.h[1]
  smull2 v3.4s, v8.8h, v9.h[1]
  smull2 v4.4s, v8.8h, v9.h[1]
  smull2 v5.4s, v8.8h, v9.h[1]
  smull2 v6.4s, v8.8h, v9.h[1]
  smull2 v7.4s, v8.8h, v9.h[1]
  movi v8.16b, 9
  movi v9.16b, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)aaaccfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200581501200412580100100800001008000050064000020020020039200399973399978010020080000200160000200392003911802011009910010080000100000511041632200360800001002004020040200402004020040
802042003915000412580100110800001008000050064000020020020039200399973399978010020080000200160000200392003911802011009910010080000100000511031633200360800001002004020040200402004020040
8020420039150210412580100100800001008000050064000020020020039200399973399978010020080000200160000200392003911802011009910010080000100000511031632200360800001002004020040200402004020040
802042003915000412580100100800001008000050064000020020020039200399973399978010020080000200160000200392003911802011009910010080000100000511031633200360800001002004020040200402004020040
8020420039150902122580100100800001008000050064000020020020039200399973399978010020080000200160000200392003911802011009910010080000100000511031683200360800001002004020040200402004020040
802042003915000412580100100800001008000050064000020020020039200399973399978010020080000200160000200392003911802011009910010080000100000511011632200360800001002004020040200402004020040
8020420039150005162580100100800001008000050064000020020020039200399973399978010020080000200160000200392003911802011009910010080000100000511041632200360800001002004020040200402004020040
80204200391501500412580100100800001008000050064000020020020039200399973399978010020080000200160000200392003911802011009910010080000100000511021633200360800001002004020040200402004020040
802042003915000412580100100800001008000050064000020020020039200399973399978010020080000200160000200392003911802011009910010080000100000511031632200360800001002004020040200402004020040
802042003915000412580100100800001008000050064000020020320039200399973399978010020080000200160000200392003911802011009910010080000100000511021623200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200481501294025800101080000108000050640000020020200392003999960310019800102080000201600002003920039118002110910108000010015020116112003680000102004020040200402004020040
800242003915004025800101080000108000050640000020020200392003999960310019800102080000201600002003920039118002110910108000010005020116212003680000102004020040200402004020040
8002420039150032525800101080000108000050640000120020200392003999960310019800102080000201600002003920039118002110910108000010005020116112003680000102004020040200402004020040
8002420039150274025800101080000108000050640000020020200392003999960310019800102080000201600002003920039118002110910108000010005020116112003680000102004020040200402004020040
80024200391503124025800101080000108000050640000020020200392003999960310019800102080000201600002003920039118002110910108000010005020116112003680000102004020040200402004020040
800242003915004025800101080000108000050640000120020200392003999960310019800102080000201600002003920039118002110910108000010005020116112003680000102004020040200402004020040
8002420039150574025800101080000108000050640000120020200392003999960310019800102080000201600002003920039118002110910108000010005020116112003680000102004020040200402004020040
8002420039150124025800101080000108000050640000020020200392003999960310019800102080000201600002003920039118002110910108000010005020116112003680000102004020040200402004020040
800242003915004025800101080000108000050640000020020200392003999960310019800102080000201600002003920039118002110910108000010005020116112003680000102004020040200402004020040
800242003915004025800101080000108000050640000020020200392003999960310019800102080000201600002003920039118002110910108000010005020116112003680000102004020040200402004020040